QG5000XSL9TH Datasheet, PDF (312/458 Pages) Intel Corporation – Intel 5000X Chipset Memory Controller Hub (MCH)

Functional Description
5.3.3
5.3.3.1
5.3.3.1.1
5.3.3.2
FB-DIMM Memory Operating Modes
The MCH supports two major modes of operation, mirrored and non-mirrored.
Non-Mirrored Mode Operation
When operating in non-mirrored mode the MCH operates the two branches
independently. In non-mirrored mode the full MCH address space of 64GB is available.
Normally when operating in non-mirrored mode both channels on a branch are
operated in lock step, referred to as dual-channel mode. There is a single DIMM, single
channel mode of operation referred to as single-channel mode.
Non-Mirrored Mode ECC
ECC is supported differently for each of these single- and dual-channel modes:
Dual-Channel Mode:
When branches operate in dual-channel mode, the MCH supports the 18 device DRAM
failure correction code option for FB-DIMM. As applied by Intel 5000X chipset MCH, this
code has the following properties:
• Correction of any x4 or x8 DRAM device failure
• Detection of 99.986% of all single bit failures that occur in addition to a x8 DRAM
failure. The MCH will detect a series of failures on a specific DRAM and use this
information in addition to the information provided by the code to achieve 100%
detection of these cases.
• Detection of all two wire faults on the DIMMs. This includes any pair of single bit
errors.
• Detection of all permutations of two x4 DRAM failures.
Single-Channel Mode:
When the branch operates in single-channel/single-DIMM mode, the MCH employs x8
SDDC as in the dual channel case. However, in this case, the ECC RAS feature set is
limited for the single DIMM memory subsystem. In the single DIMM mode (for
example, nine x8 devices), the SDDC cannot correct single wire fault (stuck-at) errors
or permanent full device errors. This is because the error correction capability in the
SDDC is limited to adjacent symbol errors on a 16-bit boundary and in the single DIMM
mode with a Burst Length of 8, there are 4 transfers of 8B to form a 32B codeword.
Hence a single wire failure in the same device is replicated across all 4 symbols
hampering the error correction. The SDDC can detect most x4/x8 DRAM failures but it
can only correct adjacent symbol errors that occur within a 16-bit boundary of each
codeword
Mirrored Mode Operation
Memory Mirroring MCH is a user-selectable feature. Mirrored mode provides for
complete recovery from a DIMM device failure. The mirroring feature is fundamentally
a way for hardware to maintain two copies of all data in the memory subsystem, such
that a hardware failure or uncorrectable error is no longer fatal to the system. When an
uncorrectable error is encountered during normal operation, hardware simply retrieves
the “mirror” copy of the corrupted data, and no system failure will occur unless both
primary and mirror copies of the same data are corrupt simultaneously (statistically
very unlikely).
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Intel^® 5000X Chipset Memory Controller Hub (MCH) Datasheet