QG5000XSL9TH Datasheet, PDF (363/458 Pages) Intel Corporation – Intel 5000X Chipset Memory Controller Hub (MCH)

Functional Description
3.3V must always be at least 0.7V greater than 1.5V. Duration of the power ramp must be between
0.1 ms and 100 ms.
5.15.2
MCH Reset Types
The Intel 5000X chipset MCH differentiates among five types of reset as defined in
table Table 5-18.
Table 5-18. MCH Reset Classes
Type
Power-Good
Hard
Processor-
only
Targeted
BINIT#
Mechanism
PwrGd Input Pin
RSTIN# Input Pin,
Configuration Write
Configuration Write
Configuration Write
Internal Error
Handling Propagated
via FSB BINIT# pin
Effect / Description
Propagated throughout the system hierarchy. Resets all logic and state
machines, and initializes all registers to their default states (sticky and
non-sticky). Tri-states all MCH outputs, or drives them to “safe” levels.
Propagated throughout the system hierarchy. Resets all logic and state
machines, and initializes all non-sticky registers to their default states.
Tri-states all MCH outputs, or drives them to “safe” levels.
Propagated to all processors via the FSBxRERSET# pins on the FSB.
The MCH does not undergo an internal reset.
Propagated down the targeted PCI Express port hierarchy. Treated as
a “Hard” reset by all affected components, clearing all machine state
and non-sticky configuration registers.
Propagated to all FSB attached components (the MCH and up to two
processors). Clears the IOQ, and resets all FSB arbiters and state
machines to their default states. Not recoverable.
5.15.2.1 Power-Good Mechanism
The initial boot of a Intel 5000X chipset MCH platform is facilitated by the Power-Good
mechanism. The voltage sources from all platform power supplies are routed to a
system component which tracks them as they ramp-up, asserting the platform “PwrGd”
signal a fixed interval (nominally 2mS) after the last voltage reference has stabilized.
There are no requirements within the MCH regarding the precise sequencing of power-
supply ramps, thus the platform should initialize properly regardless of the order in
which supplies stabilize.
Both the Intel 5000X chipset MCH and the Intel 631xESB/632xESB I/O Controller Hub
receive the system PwrGd signal via dedicated pins as an asynchronous input, meaning
that there is no assumed relationship between the assertion or deassertion of PwrGd
and any system reference clock. When PwrGd is deasserted all platform subsystems
are held in their reset state. This is accomplished by various mechanisms on each of
the different interfaces. The MCH will hold itself in a power-on reset state when PwrGd
is deasserted. The Intel 631xESB/632xESB I/O Controller Hub is expected to assert its
PCIRST# output and maintain its assertion for 1mS after power is good. The PCIRST#
output from Intel 631xESB/632xESB I/O Controller Hub is expected to drive the
RSTIN# input pin on the Intel 5000X chipset MCH, which will in turn hold the processor
complex in reset via assertion of the FSBxRESET# FSB signals.
The PCI Express attached devices and any hierarchy of components underneath them
are held in reset via implicit messaging across the PCI Express interface. The MCH is
the root of the hierarchy, and will not engage in link training until power is good and the
internal “hard” reset has deasserted.
A PwrGd reset will clear all internal state machines and logic, and initialize all registers
to their default states, including “sticky” error status bits that are persistent through all
other reset classes. To eliminate potential system reliability problems, all devices are
also required to either tri-state their outputs or to drive them to “safe” levels during a
power-on reset.
Intel^® 5000X Chipset Memory Controller Hub (MCH) Datasheet
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