QG5000XSL9TH Datasheet, PDF (365/458 Pages) Intel Corporation – Intel 5000X Chipset Memory Controller Hub (MCH)

Functional Description
5.15.4
5.15.5
Under normal operating conditions it should not be necessary to initiate targeted resets
to downstream devices, but the mechanism is provided to recover from combinations
of fatal and uncorrectable errors which compromise continued link operation.
BINIT# Mechanism
The BINIT# mechanism is provided to facilitate processor handling of system errors
which result in a hang on the FSB. The Machine Check Architecture (MCA) code
responding to an error indication, typically IERR# or MCERR#, will cause an attempt to
interrogate the MCH for error status, and if that FSB transaction fails to complete the
processor will automatically time out and respond by issuing a BINIT# sequence on the
FSB.
When BINIT# is asserted on the FSB, all bus agents (CPUs and MCH) are required to
reset their internal FSB arbiters and all FSB tracking state machines and logic to their
default states. This will effectively “un-hang” the bus to provide a path into chipset
configuration space. Note that the MCH device implements “sticky” error status bits,
providing the platform software architect with free choice between BINIT# and a
general hard reset to recover from a hung system.
Although BINIT# will not clear any configuration status from the system, it is not a
recoverable event from which the platform may continue normal execution without first
running a hard reset cycle. To guarantee that the FSB is cleared of any hang condition,
the MCH will clear all pending transaction states within its internal buffers. This applies
to outstanding FSB cycles as required, but also to in-flight memory transactions and
inbound transactions. The resulting state of the platform will be highly variable
depending upon what precisely got wiped-out due to the BINIT# event, and it is not
possible for hardware to guarantee that the resulting state of the machine will support
continued operation. What the MCH will guarantee is that no subordinate device has
been reset due to this event (PCI Express links will remain “up”), and that no internal
configuration state (sticky or otherwise) has been lost. The MCH will also continue to
maintain main memory via the refresh mechanism through a BINIT# event, thus
machine-check software will have access not only to machine state, but also to
memory state in tracking-down the source of the error.
Reset Sequencing
Figure 5-27, “Power-On Reset Sequence” on page 366 contains a timing diagram
illustrating the progression through the power-on reset sequence. This is intended as a
quick reference for system designers to clarify the requirements of the MCH.
Note the breaks in the clock waveform at the top of Figure 5-27, which are intended to
illustrate further elapsed time in the interest of displaying a lengthy sequence in a
single picture. Each of the delays in the reset sequence is of fixed duration, enforced by
either the MCH or the Intel 631xESB/632xESB I/O Controller Hub. In the case of a
power-on sequence, the MCH internal “hard” and “core” resets deassert
simultaneously. The two lines marked with names beginning “HLA” illustrate the ESI
special cycle handshake between the MCH and the Intel 631xESB/632xESB I/O
Controller Hub to coordinate across the deasserting edge of the FSBxRESET# output
from the MCH.
Table 5-19 summarizes the durations of the various reset stages illustrated above, and
attributes the delays to the component that enforces them.
The fixed delays provide time for subordinate PLL circuitry to lock on interfaces where
the clock is withheld or resynchronized during the reset sequence.
Intel^® 5000X Chipset Memory Controller Hub (MCH) Datasheet
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