QG5000XSL9TH Datasheet, PDF (219/458 Pages) Intel Corporation – Intel 5000X Chipset Memory Controller Hub (MCH)

Register Description
3.9.22.10 NRECMEMA - Non-Recoverable Memory Error Log Register A
This register latches information on the first detected fatal memory error.
Device:
Function:
Offset:
Version:
16
1
BEh
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Bit
15
14:12
11
Attr
RV
ROST
ROST
10:8
7:0
ROST
ROST
Default
0
0h
0
0h
00h
Description
Reserved
BANK: Bank of the failed request
RDWR
‘0’ = Read
‘1’ = Write
RANK: Rank of the failed request
REC_FBD_DM_BUF_ID: DM Buffer ID of the failed request
3.9.22.11 NRECMEMB - Non-Recoverable Memory Error Log Register B
This register latches information on the first detected fatal memory error.
Device:
Function:
Offset:
Version:
16
1
C0h
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Bit
31:28
27:16
15
14:0
Attr
RV
ROST
RV
ROST
Default
0h
000h
0
0h
Description
Reserved
CAS: CAS address of the failed request
Reserved
RAS: RAS address of the failed request
3.9.22.12 NRECFGLOG - Non-Recoverable DIMM Configuration Access Error Log
Register
This register latches information on the first detected non-fatal DIMM configuration
register access.
Device:
Function:
Offset:
Version:
16
1
C4h
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Bit
31:28
27:24
23:16
15:12
11
Attr
RV
ROST
ROST
RV
ROST
10:8
7:0
ROST
ROST
Default
0h
0h
00h
0h
0
0h
00h
Description
Reserved
BE: Byte Enables of the failed request
REG: Register Address of the failed request
Reserved
RDWR
‘0’ = Read
‘1’ = Write
FUNCTION: Function Number of the failed request
CFG_FBD_DM_BUF_ID: DM Buffer ID of the failed request
Intel^® 5000X Chipset Memory Controller Hub (MCH) Datasheet
219