QG5000XSL9TH Datasheet, PDF (129/458 Pages) Intel Corporation – Intel 5000X Chipset Memory Controller Hub (MCH)

Register Description
3.8.8.31
PEXCTRL2[7:2,0]: PCI Express Control Register 2
This is an auxiliary control register for PCI Express port specific debug/defeature
operations.
3.8.8.32
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
0, 2-3
0
4Ch
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
4-5
0
4Ch
Intel 5000Z Chipset
4-7
0
4Ch
Intel 5000P Chipset
Bit
Attr
Default
Description
7:1
RV
0
RW
0
Reserved.
0
NO_COMPLIANCE:
Set by software to enable link operation in the presence of single wire failures
on the link. If clear, then specified link behavior in the presence of a wire failure
will be Polling.Compliance.
PEXCTRL3[7:2,0] - PCI Express Control Register 3
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
0, 2-3
0
4Dh
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
4-5
0
4Dh
Intel 5000Z Chipset
4-7
0
4Dh
Intel 5000P Chipset
Bit
Attr
Default
Description
7:5
RV
4
RWO
3:0
RV
0
Reserved.
1
PORTENABLE: PCI Express port enable control
1: The PCI Express port can be enabled by software and is available for
use.
0: The PCI Express port is disabled and not available. This setting disables
the underlying port logic and associated PCI Express x4 lanes, completely
removing the port from register configuration space.
0
Reserved
This is an additional control register for PCI Express port specific debug/defeature
operations for RAS.
Intel^® 5000X Chipset Memory Controller Hub (MCH) Datasheet
129