QG5000XSL9TH Datasheet, PDF (204/458 Pages) Intel Corporation – Intel 5000X Chipset Memory Controller Hub (MCH)

Register Description
3.9.14
GRHOSTFULLCFG: Host Full Flow Control Configuration
This register configures flow control when the host is full. It primarily effects the
Southbound data path and determines when the flow control signal to the core is
asserted.
Device:
Function:
Offset:
16
1
16Dh
Bit
Attr
Default
7:0 RWST
0h
Description
FCMUX: Flow Control Mux Selector
Configures Flow control on the host according to Table 3-42. This primarily
affect the 5:4 gearing ratio.
Table 3-42. FB-DIMM to Host Flow Control Mux Select
FSB:Memory Frequency
Gear Ratio¹
Value
333:333
1:1
00h
267:267
400:400
333:267
5:4
02h
267:333
4:5 (conservative)
02h
267:333
4:5 (aggressive)
08h
Notes:
1. For 4:5 gear ratio, software should use either conservative or aggressive mode for all the
respective memory gearing registers (no mix and match).
3.9.15 GRBUBBLECFG: FB-DIMM Host Bubble Configuration
This register provides valid signals to assert data in the FB-DIMM side for various
gearing ratios. This primarily affects the Northbound data path for the 5:4 configuration
and determines when a bubble is inserted when gearing up.
.
Device:
Function:
Offset:
Version:
16
1
16Eh
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Bit
Attr
Default
Description
7:0 RWST
0h
FBDBBLMUX: FB-DIMM Data Bubble Mux selector.
Configures bubbles in the host according to Table 3-43. This primarily affect
the 5:4 gearing ratio.
Table 3-43. FB-DIMM Bubble Mux Select
FSB:Memory Frequency
Gear Ratio
333:333
1:1
267:267
400:400
333:267
5:4
267:333
4:5
Notes:
1. Ignored by Mgr registers in 4:5 mode.
Value
00h
04h
00h¹
204
Intel^® 5000X Chipset Memory Controller Hub (MCH) Datasheet