QG5000XSL9TH Datasheet, PDF (190/458 Pages) Intel Corporation – Intel 5000X Chipset Memory Controller Hub (MCH)

Register Description
3.8.13.19 FERR_NF_INT - Internal First Non-Fatal Error Register
Device:
Function:
Offset:
Version:
16
2
C1h
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Bit
Attr
Default
Description
7:3
RV
2
RWCST
1
RWCST
0
RWCST
0h
Reserved
0
B8Err: SF Coherency Error for BIL (SF)
0
B6Err: Single ECC error on SF lookup (SF)
0
B5Err: Single Address Map Error (COH)
3.8.13.20 NERR_FAT_INT - Internal Next Fatal Error Register
Device:
Function:
Offset:
Version:
16
2
C2h
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Bit
Attr
Default
Description
7:5
RV
4
RWCST
3
RV
2
RWCST
1
RWCST
0
RWCST
000
Reserved
0
B7Err: Multiple ECC error in any of the ways during SF lookup (SF)
0
Reserved
0
B3Err: Coherency Violation Error (COH) for EWB
0
B2Err: Multi-Tag Hit SF (SF)
0
B1Err: DM Parity Error (DM)
3.8.13.21 NERR_NF_INT - Internal Next Non-Fatal Error Register
Device:
Function:
Offset:
Version:
16
2
C3h
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Bit
Attr
Default
Description
7:3
RV
2
RWCST
1
RWCST
0
RWCST
0h
Reserved
0
B8Err: SF Coherency Error for BIL (SF)
0
B6Err: Single ECC error on SF lookup (SF)
0
B5Err: Address Map Error (COH)
3.8.13.22 NRECINT - Non Recoverable Internal MCH Error Log Register
This register will log non-recoverable errors (Fatal and Non Fatal) based on the internal
MCH errors that originate from the FERR_FAT_INT, FERR_NF_INT described starting
from Section 3.8.13.18. For debugging VPP errors in this register, for example, if
VPP_PEX_PORT2-3 is set, then software can scan the PCI Express configuration space
for unit errors logged in the device 2,3 for PEX_UNIT_FERR/NERR register as defined in
Section 3.8.12.28 to determine the failing port. The same can be repeated for the
FB-DIMM Channels when VPP_FBD is set.
190
Intel^® 5000X Chipset Memory Controller Hub (MCH) Datasheet