QG5000XSL9TH Datasheet, PDF (228/458 Pages) Intel Corporation – Intel 5000X Chipset Memory Controller Hub (MCH)

Register Description
Figure 3-6. FB-DIMM Reset Timing
FBDCLK
ENABLED
FBD PLL
T₁
UNLOCKED
LOCKED
CORERESET#
0
21ns
2us
3ns
SOFTCORERESET#
3.9.23.5
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
21
0
53h
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
22
0
53h
Intel 5000P Chipset
Bit Attr
7: RV
3
2 RWST
1 RWST
0 RWST
Default
00h
Reserved
Description
0
BRSELCMPRESET: Branch Select for Compensation Reset
0: COMPreset is tied to CORERESET# from branch 0
1: COMPreset is tied to CORERESET# from branch 1
For Branch 1 to be selected for reset, this field has to be a ‘1’ for both branch
instances.
0
SOFTCORERESET#: Soft Core Reset
See Timing diagram Figure 3-6.
0: Soft Core Reset Asserted
1: Soft Core Reset De-Asserted
0
CORERESET#: Core Reset
See Timing diagram Figure 3-6.
0: Core Reset Asserted
1: Core Reset De-Asserted
SPCPC[1:0] - Spare Copy Control
These controls set up sparing for each branch. Branch zero (device 21) takes
precedence over branch one (device 22): if both spare-control-enabled branches’ spare
error thresholds trigger in the same cycle, sparing will only commence on branch zero.
Sparing will not commence on a competing branch until its in-progress competitor’s
spare control enable is cleared and it’s UERRCNT/CERRCNT criteria is still met.
228
Intel^® 5000X Chipset Memory Controller Hub (MCH) Datasheet