QG5000XSL9TH Datasheet, PDF (179/458 Pages) Intel Corporation – Intel 5000X Chipset Memory Controller Hub (MCH)

Register Description
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
0, 2-3
0
15Ch
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
4-5
0
15Ch
Intel 5000Z Chipset
Device:
Function:
Offset:
Version:
4-7
0
15Ch
Intel 5000P Chipset
Bit
31:13
12
11
10
9
8
7
6
5
4
3
Attr
RV
RWCST
RWCST
RWCST
RWCST
RWCST
RWCST
RWCST
RWCST
RWCST
RWCST
2
RWCST
1
RWCST
0
RWCST
Default
0h
0
0
0
0
0
0
0
0
0
0
0
0
0
Description
Reserved
Next_FAT_Err_IO19: Surprise Link Down
Next_FAT_Err_IO18: ESI Reset time-out
Next_FAT_Err_IO9: PEX - Malformed TLP
Next_FAT_Err_IO10: PEX - Receive Buffer Overflow Error
Next_FAT_Err_IO8: PEX - Unexpected Completion Error
Next_FAT_Err_IO7: PEX - Completer Abort
Next_FAT_Err_IO6: PEX - Completion Timeout
Next_FAT_Err_IO5: PEX - Flow Control Protocol Error
Next_FAT_Err_IO4: PEX - Poisoned TLP
Next_FAT_Err_IO3: PEX - Training Error
This field should not be used for setting Training error severity due to a
recent PCI-SIG ECN (Jan 22, 04) to remove training error. Hardware
behavior is undefined.
Next_FAT_Err_IO2: PEX - Received Unsupported Request
Next_FAT_Err_IO1: PEX - Received Fatal Error Message
Next_FAT_Err_IO0: PEX - Data Link Layer Protocol Error
3.8.12.27 PEX_NF_COR_NERR[7:2, 0] - PCI Express Non Fatal or Correctable
Next Error Register
These errors are written by the MCH if the respective bits are set in PEX_NF_COR_FERR
register. This register records the subsequent occurrences of unmasked PCI Express
NON-FATAL (Uncorrectable) and CORRECTABLE errors.
Intel^® 5000X Chipset Memory Controller Hub (MCH) Datasheet
179