QG5000XSL9TH Datasheet, PDF (293/458 Pages) Intel Corporation – Intel 5000X Chipset Memory Controller Hub (MCH)

System Address Map
The Intel 5000P Chipset prevents illegal processor access to SMM memory. This is
accomplished by routing memory requests from processors as a function of transaction
request address, code or data access, the SMMEM# signal accompanying request and
the settings of the Intel 5000P Chipset MCH.SMRAMC, Intel 5000P Chipset
MCH.EXSMRC, and Intel 5000P Chipset MCH.BCTRL registers. Table 4-9 defines Intel
5000P Chipset MCH’s routing for each case. Illegal accesses are either routed to the ESI
bus where they are Master Aborted or are blocked with error flagging. SMMEM# only
affects Intel 5000P Chipset behavior if it falls in an enabled SMM space. Note that the
D_CLS only applies to the legacy (A_0000-B_FFFF) SMM region. The bold values
indicate the reason SMM access was granted or denied.
Note:
If a spurious inbound access targets the enabled SMM range (viz., legacy, High SMM
Memory and Extended SMRAM (T-segment)), then it will be Master-aborted. The
EXSMRAMC.E_SMERR register field (Invalid SMRAM) is set for accesses to the High
SMM Memory and Extended SMRAM (T-segment)). Refer to Table 4-10.
Table 4-9. Decoding Processor Requests to SMM and VGA Spaces
SMM region
Transaction
Address
Range
SMM Memory
Address
Range
SMM
Access
Control
1
Routing
Legacy
A_0000h
A_0000h
x
VGA/SMM ² to
to
yes
B_FFFFh
B_FFFFh
no
yes
Extended
SMRAM
(TSEG)
ESMMTOP -TSEG_SZ ESMMTOP -TSEG_SZ x
to
to
x
ESMMTOP
ESMMTOP
yes
no
no
High SMM FEDA_0000h
A_0000h
x
to
to
x
FEDB_FFFFh
B_FFFFh
yes
no
no
0 x x x to the VGA-enabled port (in
1
1
x
x
BCTRL);
otherwise, ESI³
1xxx
1 0 x x to SMM memory
0 x x x to identical system memory
1
x
0
x
by definition
1 x 1 x to SMM memory
1x11
1 x 1 0 block access: master abort
set EXSMRAMC.E_SMERR
0 x x x to ESI (where access will be
1
0
x
x
master aborted)
1
1
x
x
to SMM memory⁴
11x1
1 1 x 0 block access: master abort
set EXSMRAMC.E_SMERR
Notes:
1. SMM memory access control, see Table 4-8.
2. Software must not cache this region.
3. One and only one BCTRL can set the VGAEN; otherwise, send to ESI.
4. Notice this range is mapped into legacy SMM range (A_0000h to B_FFFFh).
4.4.3
Inbound Transactions
In general, inbound I/O transactions are decoded and dispositioned similarly to
processor transactions. The key differences are in SMM space, memory mapped
configuration space, and interrupts. Inbound transaction targeting at itself will be
master aborted.
Note that inbound accesses to the SMM region must be handled in such a way that FSB
snooping and associated potential implicit writebacks are avoided. This is necessary to
prevent compromising SMM data by returning real content to the I/O subsystem. Note
also that DMA engine is treated as an I/O device, thus accesses initiated by the DMA
engine are considered as inbound accesses.
Intel^® 5000X Chipset Memory Controller Hub (MCH) Datasheet
293