QG5000XSL9TH Datasheet, PDF (209/458 Pages) Intel Corporation – Intel 5000X Chipset Memory Controller Hub (MCH)

Register Description
3.9.21.2
MIR[2:0] - Memory Interleave Range
These registers define each memory branch’s interleave participation in processor-
physical (A) space.
Each register defines a range. If the processor-physical address falls in the range
defined by an MIR, the “way” fields in that MIR defines branch participation in the
interleave. The way-sensitive address bit is A[6]. For a MIR to be effective, WAY0 and
WAY1 fields can not be set to 00b. In mirror mode, the WAY0 and WAY1 fields should
be set to 11b. Matching addresses participate in the corresponding ways.
Compensation for a non-4GB MMIO gap size is performed by adjusting the limit of each
range upward if it is above TOLM as shown in Table 3-47.
MIR updates can only occur in the RESET, READY, FAULT, DISABLED, RECOVERYRESET,
RECOVERYFAULT, and RECOVERYREADY states.
Table 3-47. Interleaving of an address is governed by MIR[i]
Limit with respect to TOLM
Match MIR[i]
if MIR[i].LIMIT[7:0] <= TOLM
then MIR[i].LIMIT[7:0] > A[35:28] >= MIR[i-
1].LIMIT[7:0]
if MIR[i].LIMIT[7:0] > TOLM > MIR[i-1].LIMIT[7:0] then MIR[i].LIMIT[7:0] + (10H - TOLM) > A[35:28] >=
MIR[i-1]¹.LIMIT[7:0]
if MIR[i].LIMIT[7:0] > MIR[i-1].LIMIT[7:0] >=
TOLM
then MIR[i].LIMIT[7:0] + (10H - TOLM) > A[35:28] >=
MIR[i-1].LIMIT[7:0] + (10H - TOLM)
Notes:
1. For MIR[0], MIR[i-1] is defined to be 0.
3.9.21.3
Device:
Function:
Offset:
Version:
16
1
88h, 84h, 80h
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Bit
15:4
Attr
RW
3:2
RV
1
RW
0
RW
Default
000h
00
0
0
Description
LIMIT
This field defines the highest address in the range A[39:28] prior to
modification by the TOLM register. Since MIRs only comprehend 64GB -
(TOLM.TOLM * 256 MB) of address space, LIMIT[11:8] (bits [15:12] of this
register) are ignored, and the largest legal value is (64 GB - (TOLM.TOLM *
256 MB)) / 2²⁸.
Reserved
WAY1
Branch 1 participate in this MIR range if this bit is set AND (the way-sensitive
bit is 1b OR WAY0 of this MIR is 0b).
WAY0
Branch 0 participate in this MIR range if this bit is set AND (the way-sensitive
bit is 1b OR WAY1 of this MIR is 0b).
AMIR[2:0] - Adjusted Memory Interleave Range
For the convenience of software which is trying to determine the physical location to
which a processor bus address is sent, 16 scratch bits are associated with each MIR.
Intel^® 5000X Chipset Memory Controller Hub (MCH) Datasheet
209