QG5000XSL9TH Datasheet, PDF (317/458 Pages) Intel Corporation – Intel 5000X Chipset Memory Controller Hub (MCH)

Functional Description
The Intel 5000X chipset MCH MCH integrates a 100KHz SPD controller to access the
DIMM SPD EEPROM’s. There are four SPD ports. SPD0SMBDATA, and SPD0SMBCLK are
defined for channel 0; SPD1SMBDATA, and SPD1SMBCLK are defined for channel 1;
SPD2SMBDATA, and SPD2SMBCLK are defined for channel 2; and SPD3SMBDATA, and
SPD3SMBCLK are defined for channel 3. There can be a maximum of eight SPD
EEPROM’s associated with each SPD bus. Therefore, the SPD interface is wired as
indicated in Figure 5-8.
Figure 5-8. Connection of DIMM Serial I/O Signals
SLOT 3
SLOT 2
SLOT 1
SLOT 0
SA0
SA1
SA2
SA0
SA1
SA2
SA0
SA1
SA2
SA0
SA1
SA2
CHANNEL
0
D IM M
D IM M
D IM M
D IM M
CHANNEL
1
D IM M
D IM M
D IM M
D IM M
SA0 SA0
SA1 SA1
SA2 SA2
SA0 SA0
SA1 SA1
SA2 SA2
SA0 SA0
SA1 SA1
SA2 SA2
SA0 SA0
SA1 SA1
SA2 SA2
CHANNEL
2
D IM M
D IM M
D IM M
D IM M
CHANNEL
3
D IM M
D IM M
D IM M
D IM M
SA0
SA1
SA2
SA0
SA1
SA2
SA0
SA1
SA2
SA0
SA1
SA2
SCL1/ SCL2/
SDA1 SDA2
SCL0/ SCL3/
SDA0 SDA3
Intel® 5000P
C hipset
Board layout must map chip selects to SPD Slave Addresses as shown in Table 5-7. The
slave address is written to the SPDCMD configuration register (see Section 3.9.26.2).
Table 5-7.
SPD Addressing
SPD Bus
0
FB-DIMM
Channel
0
1
1
2
2
3
3
SLOT Slave Address
0
0
1
1
2
2
3
3
0
0
1
1
2
2
3
3
0
0
1
1
2
2
3
3
0
0
1
1
2
2
3
3
Intel^® 5000X Chipset Memory Controller Hub (MCH) Datasheet
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