QG5000XSL9TH Datasheet, PDF (377/458 Pages) Intel Corporation – Intel 5000X Chipset Memory Controller Hub (MCH)

Functional Description
Figure 5-41. SMBus Configuration Write (Word Writes, PEC Enabled)
S 11X0_XXX W A Cmd = 10011101 A
Bus Number
A Device/Function A
PEC
AP
S
11X0_XXX
W A Cmd = 00011101 A
Register[15:8]
A
Register[7:0]
A
PEC
AP
S 11X0_XXX W A Cmd = 00011101 A
Data[31:24]
A
Data[23:16]
A
PEC
AP
S 11X0_XXX W A Cmd = 01011101 A
Data[15:8]
A
Data[7:0]
A
PEC
AP
Figure 5-42. SMBus Configuration Write (Write Bytes, PEC Enabled)
S
11X0_XXX
WA
Cmd = 10011100
A
Bus Number
A
S
11X0_XXX
WA
Cmd = 00011100
A
D e vic e /F u n c tio n
A
S
11X0_XXX
WA
Cmd = 00011100
A
R e g is te r[1 5 :8 ]
A
S
11X0_XXX
WA
Cmd = 00011100
A
R e g is te r[7 :0 ]
A
S
11X0_XXX
WA
Cmd = 00011100
A
D a ta [3 1 :2 4 ]
A
S
11X0_XXX
WA
Cmd = 00011100
A
D a ta [2 3 :1 6 ]
A
S
11X0_XXX
WA
Cmd = 00011100
A
D a ta [1 5 :8 ]
A
S
11X0_XXX
WA
Cmd = 01011100
A
D a ta [7 :0 ]
A
PEC
PEC
PEC
PEC
PEC
PEC
PEC
PEC
AP
AP
AP
AP
AP
AP
AP
AP
5.16.4.4
5.16.4.5
Note:
SMBus Error Handling
The SMBus slave interface handles two types of errors: Internal and PEC. For example,
internal errors can occur when the Intel 5000P Chipset issues a configuration read on
the PCI Express port that read’s terminates in error. These errors manifest as a not-
acknowledge (NAK) for the read command (End bit is set). If an internal error occurs
during a configuration write, the final write command receives a NAK just before the
stop bit. If the master receives a NAK, the entire configuration transaction should be
reattempted.
If the master supports Packet Error Checking (PEC) and the PEC_en bit in the command
is set, then the PEC byte is checked in the slave interface. If the check indicates a
failure, then the slave will NAK the PEC packet.
SMBus Interface Reset
• The slave interface state machine can be reset by the master in two ways:
• The master holds SCL low for 25 ms cumulative. Cumulative in this case means
that all the “low time” for SCL is counted between the Start and Stop bit. If this
totals 25 ms before reaching the Stop bit, the interface is reset.
• The master holds SCL continuously high for 50 ms.
Since the configuration registers are affected by the reset pin, SMBus masters will not
be able to access the internal registers while the system is reset.
Intel^® 5000X Chipset Memory Controller Hub (MCH) Datasheet
377