QG5000XSL9TH Datasheet, PDF (208/458 Pages) Intel Corporation – Intel 5000X Chipset Memory Controller Hub (MCH)

Register Description
3.9.20
ERRPER - Error Period
Non-zero UERRCNT and CERRCNT counts are decremented when the error period
counter reaches this threshold. The error period counter is cleared on reset or when it
reaches this threshold. The error period counter increments every 32,768 cycles.
Table 3-46 indicates the timing characteristics of this register:
Table 3-46. Timing Characteristics of ERRPER
Core Frequency
333 MHz
266 MHz
Per Increment
98.304us
122.880us
Maximum Period
4 days, 21 hours, 16 minutes, 52.465056596 seconds
6 days, 2 hours, 36 minutes, 5.581331712 seconds
3.9.21
3.9.21.1
Device:
Function:
Offset:
Version:
16
1
50h
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Bit
31:0
Attr
RW
Default
0h
Description
THRESH: UERRCNT / CERRCNT decrement threshold.
Memory Map Registers
TOLM - Top Of Low Memory
This register defines the low MMIO gap below 4GB. See Section 3.9.21.2.
Whereas the MIR.LIMITs are adjustable, TOLM establishes the maximum address below
4 GB that should be treated as a memory access. TOLM is defined in a 256 MB
boundary.
This register must not be modified while servicing memory requests.
Device:
Function:
Offset:
Version:
16
1
6Ch
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Bit
15:12
Attr
RW
11:0 RV
Default
1h
000h
Description
TOLM: Top Of Low Memory
This register defines the maximum DRAM memory address that lies below
4GB.
Addresses equal to or greater than the TOLM, and less than 4G, are decoded
as low MMIO, MMCFG (if map within this range by HECBASE), chipset,
interrupt/SMM and firmware as described in the address mapping chapter. All
accesses less than the TOLM are treated as DRAM accesses (except for the
VGA region when enabled and PAM gaps).
Configuration software should set this field either to maximize the amount of
memory in the system (same as the top MIR.LIMIT), or to minimize the
allocated space for the lower PCI memory (low MMIO) plus 32 MB (chipset/
interrupt/SMM and firmware) at a 256 MB boundary.
This field must be set to at least 1h, for a minimum of 256 MB of DRAM. There
is also a minimum of 256MB between TOLM and 4 GB (for low MMIO, MMCFG,
chipset, interrupt/SMM and firmware) since TOLM is on a 256MB boundary.
This field corresponds to A[31:28]. Setting of “1111” corresponds to 3.75 GB
DRAM, and so on down to “0001” corresponds to 0.25GB DRAM. “0000”
setting is illegal and a programming error.
Reserved
208
Intel^® 5000X Chipset Memory Controller Hub (MCH) Datasheet