QG5000XSL9TH Datasheet, PDF (259/458 Pages) Intel Corporation – Intel 5000X Chipset Memory Controller Hub (MCH)

Register Description
3.10.8.2
PMCSR - Power Management Control and Status Register
This register provides status and control information for PM events in the PCI Express port of the DMA
Engine Device.
Device:
Function:
Offset:
Version:
8
0
54h
Intel 5000P Chipset
Bit
31:24
Attr
RO
23
RO
22
RO
21:16
15
RV
RWCST
14:13
RO
12:9
RO
8
RWST
7:2
RV
1:0
RW
Default
0h
0h
0h
0h
0h
0h
0h
0h
0h
0h
Description
Data: Data
Data read out based on data select (DSEL). Refer to section 3.2.6 of PCI PM
specification for details. This is not implemented in the e Power
Management capability for Intel 5000P Chipset MCH and is hardwired to
0h.
BPCCEN: Bus Power/Clock Control Enable
This field is hardwired to 0h.
B2B3S: B2/B3 Support
This field is hardwired to 0h.
Reserved.
PMESTS: PME Status
This PME Status is a sticky bit. When set, the device generates a PME
internally independent of the PMEEN bit defined below. Software clears
this bit by writing a ‘1’.
As an integrated device within the root complex, the Intel 5000P Chipset
MCH will never set this bit, because it never generates a PME internally
independent of the PMEEN bit.
DSCL: Data Scale
This 2-bit field indicates the scaling factor to be used while interpreting the
“data_scale” field.
DSEL: Data Select
This 4-bit field is used to select which data is to reported through the “data”
and the “Data Scale” fields.
PMEEN: PME Enable
This field is a sticky bit and when set enables PMEs generated internally to
appear at the Intel 631xESB/632xESB I/O Controller Hub through the
“Assert(Deassert)_PMEGPE”message. This has no effect on the Intel
5000P Chipset MCH since it does not generate PME events internally.
Reserved.
PS: Power State
This 2-bit field is used to determine the current power state of the function
and to set a new power state as well.
00: D0
01: D1 (reserved)
10: D2 (reserved)
11: D3_hot
Intel^® 5000X Chipset Memory Controller Hub (MCH) Datasheet
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