QG5000XSL9TH Datasheet, PDF (175/458 Pages) Intel Corporation – Intel 5000X Chipset Memory Controller Hub (MCH)

Register Description
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
2-3
0
148h
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
4-5
0
148h
Intel 5000Z Chipset
Device:
Function:
Offset:
Version:
4-7
0
148h
Intel 5000P Chipset
Bit
15
14
13
12
11:6
5
4
3:1
0
Attr
RW
RW
RW
RW
RV
RW
RW
RV
RW
Default
0
0
0
0
0h
0
0
0h
0
Description
IO7DetMsk: Completer Abort Status
IO6DetMsk: Completion Time-out Status
IO5DetMsk: Flow Control Protocol Error Status
IO4DetMsk: Poisoned TLP Status
Reserved
IO19DetMsk: Surprise Link Down Mask
IO0DetMsk: Data Link Protocol Error Status
Reserved
IO3DetMsk:Training Error Status
This field should not be used for setting Training error severity due to a recent
PCI-SIG ECN (Jan 22, 04) to remove training error. Hardware behavior is
undefined.
3.8.12.22 EMASK_COR_PEX[7:2, 0] - Correctable Error Detect Mask
This register masks (blocks) the detection of the selected bits. Normally all are
detected. But software can choose to disable detecting any of the error bits.
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
0, 2-3
0
14Ch
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
4-5
0
14Ch
Intel 5000Z Chipset
Device:
Function:
Offset:
Version:
4-7
0
14Ch
Intel 5000P Chipset
Bit
31:13
12
11:9
8
7
6
5:1
Attr
RV
RW
RV
RW
RW
RW
RV
Default
0h
0
0h
0
0
0
0h
Description
Reserved
IO16DetMsk: Replay Timer Time-out Mask
Reserved
IO15DetMsk: Replay_Num Rollover Mask
IO14DetMsk: Bad DLLP Mask
IO13DetMsk: Bad TLP Mask
Reserved
Intel^® 5000X Chipset Memory Controller Hub (MCH) Datasheet
175