QG5000XSL9TH Datasheet, PDF (341/458 Pages) Intel Corporation – Intel 5000X Chipset Memory Controller Hub (MCH)

Functional Description
5.8.0.1
• Since XAPIC directed interrupts (A[3] = 0) cannot be retried, they must be
accepted. If the Intel 5000P Chipset cannot accept the interrupt, then it must
assert BPRI# until resources are available.
IPI Ordering
In a system, there are ordering requirements between IPIs and other previous
coherent and non-coherent accesses. The way the ordering is maintained is that it is
expected that the chipset will defer the previous ordered access. The chipset will not
complete the transaction until the write is “posted” or the read data is delivered. Since
the processor will not issue an ordered IPI until the previous transaction has been
completed, ordering is automatically maintained.
An example where the ordering must be maintained is if a processor writes data to
memory and issues an IPI to indicate the data has been written, subsequent reads to
the data (after the IPI) must be the updated values. (Producer consumer). For this
example, assuming cacheable memory, the chipset defers the BIL/BRIL (read for
ownership). Only after all other processor caches have been invalidated, and the
deferred reply is returned (where the cache will be written) will the subsequent IPI be
issued.
There are no ordering requirements between IPIs. There are no ordering requirements
between IPIs and subsequent request. The IPIs are claimed on the FSB (front side bus)
and are not deferred. Therefore, software must not rely on the ordered delivery
between the IPI and subsequent transactions. If ordering is needed, it must protect any
subsequent coherent and non-coherent accesses from the effects of a previous IPI
using synchronization primitives. Also, software must not rely on ordered delivery of an
IPI with respect to other IPI from the same processor to any target processor.
Intel^® 5000X Chipset Memory Controller Hub (MCH) Datasheet
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