QG5000XSL9TH Datasheet, PDF (411/458 Pages) Intel Corporation – Intel 5000X Chipset Memory Controller Hub (MCH)

Electrical Characteristics
5. Impedance during all LTSSM states. When transitioning from a Fundamental Reset to Detect (the initial state of the LTSSM)
there is a 5 ms transition time before Receiver termination values must be met on all un-configured Lanes of a Port.
6. The RX DC Common Mode Impedance that exists when no power is present or Fundamental Reset is asserted. This helps
ensure that the Receiver Detect circuit will not falsely assume a Receiver is powered on when it is not. This term must be
measured at 300 mV above the RX ground.
7.2.5 Miscellaneous DC Characteristics
Table 7-10. SMBus DC Characteristics
Symbol
Signal
Group
V_IH
(w)
V_IL
(w)
V_OL
(w)
I_OL
(w)
I_Leak
(w)
C_Pad
(w)
Notes:
1. At Vol max, Iol = max.
Parameter
Input High Voltage
Input Low Voltage
Output Low Voltage
Output Low Current
Leakage Current
Pad Capacitance
Table 7-11. JTAG DC Characteristics
Symbol
V_IH
V_IL
V_OL
I_Leak
Signal
Group
(y)
(y)
(z)
(y) (z)
Parameter
Input High Voltage
Input Low Voltage
Output Low Voltage
Leakage Current
Min
2.1
Nom
Min
0.9
Nom
Table 7-12. 1.5 V CMOS DC Characteristics
Symbol
V_IH
V_IL
V_OH
V_OL
I_Leak
V_ABS
Signal
Group
(d) (cc)
(d) (cc)
(cc)
(cc)
(cc)
(d) (cc)
Parameter
Input High Voltage
Input Low Voltage
Output High Voltage
Output Low Voltage
Leakage Current
Input Damage Thresholds
Min
1.0
-0.2
1.1
-0.2
Nom
Table 7-13. 3.3 V CMOS DC Characteristics (Sheet 1 of 2)
Symbol
V_IH
V_IL
V_OH
Signal
Group
(dd)
(dd)
(ee)
Parameter
Input High Voltage
Input Low Voltage
Output High Voltage
Min
2.1
Nom
Max
0.8
0.4
4
10
10
Unit
V
V
V
mA
μA
pF
Note
s
1
Max
0.5
0.4
2.9
Unit
V
V
V
μA
Note
s
Max
1.6
0.5
0.4
70
1.6
Unit
V
V
V
V
μA
V
Note
s
Max
0.8
Unit
V
V
V
Note
s
Intel^® 5000X Chipset Memory Controller Hub (MCH) Datasheet
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