QG5000XSL9TH Datasheet, PDF (316/458 Pages) Intel Corporation – Intel 5000X Chipset Memory Controller Hub (MCH)

Functional Description
5.3.8
Single Device Data Correction (SDDC) Support
The Intel 5000X chipset MCH employs a single device data correction (SDDC)
algorithm for the memory subsystem that will recover from a x4/x8 component failure.
The chip disable is a 32-byte two-phase code. SDDC is also supported for x4 devices.
In addition the MCH supports demand and patrol scrubbing.
A scrub corrects a correctable error in memory. A four-byte ECC is attached to each 32-
byte “payload”. An error is detected when the ECC calculated from the payload
mismatches the ECC read from memory. The error is corrected by modifying either the
ECC or the payload or both and writing both the ECC and payload back to memory.
Only one demand or patrol scrub can be in process at a time.
The attributes of the SDDC code are as follows:
• Two Phase Code over 32 bytes of data.
• 100% Correction for all single x4 or x8 component failures.
• 100% Detection of all double x4 component failures.
• Detection Characteristics for x8 double device errors are provided in the Table 5-6
Table 5-6.
x8 Double Device Detection Characteristics
Overall coverage - 99.986%
Double bit errors - 100%
Double wire faults - 100%
Wire plus single bit - 100%
Device plus single - 99.99999%
Device plus wire - 99.99998%
Device plus equal/phase - 99.9998%
Equal/phase plus equal/phase - 100%
To increase the detection coverage of a (x8 device failure + SBE), that is, to avoid silent
data corruption in the event of a particle induced error while correcting for a failed
device, the Intel 5000X chipset MCH MCH provides the following features:
• Each rank will have an encoded value of the “failed” x8 component or pair of x4
components.
• If for any given rank, the Intel 5000X chipset MCH MCH detects a correctable error
with a weight >1 and the “corrected” symbol does not match the “failed”
component then the Intel 5000X chipset MCH MCH will assume that the error is
multi-bit uncorrectable error and signal a “fatal error”.
5.3.9
FB-DIMM Memory Configuration Mechanism
Before any cycles to the memory interface can be supported, the MCH DRAM registers
must be initialized. The MCH must be configured for operation with the installed
memory types. Detection of memory type and size is accomplished via the 4 Serial
Presents Detect (System Management Bus) interfaces on the MCH (SMBus 1, 2, 3 and
4). The SMBus interfaces are two-wire buses are used to extract the DRAM type and
size information from the Serial Presence Detect port on the DIMMs.
FB-DIMMs contain a 6-pin Serial Presence Detect interface, which includes SCL (serial
clock), SDA (serial data), and SA[3:0] (serial address). Devices on the SMBus bus have
a 7-bit address. For the DIMMs, the upper three bits are fixed at 101. The lower four
bits are strapped via the SA[3:0] pins. SCL and SDA are connected to the respective
SPDxSMBDATA, SPDxSMBCLK pins on the MCH, see Figure 5-8.
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Intel^® 5000X Chipset Memory Controller Hub (MCH) Datasheet