QG5000XSL9TH Datasheet, PDF (161/458 Pages) Intel Corporation – Intel 5000X Chipset Memory Controller Hub (MCH)

Register Description
3.8.12.2
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
0, 2-3
0
100h
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
4-5
0
100h
Intel 5000Z Chipset
Device:
Function:
Offset:
Version:
4-7
0
100h
Intel 5000P Chipset
Bit
31:20
Attr
RO
19:16 RO
15:0 RO
Default
140h
1h
0001h
Description
NCAPOFF: Next Capability Offset
This field points to the next Capability in extended configuration space.
CV: Capability Version
Set to 1h for this version of the PCI Express logic
PEXCAPID: PCI Express Extended CAP_ID
Assigned for advanced error reporting
UNCERRSTS[7:2] - Uncorrectable Error Status
This register identifies uncorrectable errors detected for the PCI Express Port. If an
error occurs and is unmasked in the detect register (EMSAK_UNCOR_PEX), the
appropriate error bit will be recorded in this register. If an error is recorded in the
UNCERRSTS register and the appropriate bit (along with the severity bit of the
UNCERRSEV register) determines which bit in the PEX_FAT_FERR, PEX_NF_COR_FERR,
PEX_FAT_NERR, PEX_NF_COR_NERR register gets recorded.These error log registers
are described starting from Section 3.8.12.24.
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
2-3
0
104h
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
4-5
0
104h
Intel 5000Z Chipset
Device:
Function:
Offset:
Version:
4-7
0
104h
Intel 5000P Chipset
Bit
31:21
20
19
18
17
16
15
14
Attr
RV
RWCST
RV
RWCST
RWCST
RWCST
RWCST
RWCST
Default
0h
0
0
0
0
0
0
0
Description
Reserved
IO2Err: Received an Unsupported Request
Reserved
IO9Err: Malformed TLP Status
IO10Err: Receiver Buffer Overflow Status
IO8Err: Unexpected Completion Status
IO7Err: Completer Abort Status
IO6Err: Completion Time-out Status
Intel^® 5000X Chipset Memory Controller Hub (MCH) Datasheet
161