QG5000XSL9TH Datasheet, PDF (21/458 Pages) Intel Corporation – Intel 5000X Chipset Memory Controller Hub (MCH)

Introduction
Figure 1-1. Intel^® 5000X Chipset System Block Diagram
P1
P2
1066/1333 MTS System
Bus
4 PCI-E
X4 4GB/s
1066/1333 _{MTS System}
Bus
Channel0
5.3GB/s
PCI-E X16
Graphics Port
Channel1
5.3 GB/s
SM Buses
Note: All PCI- Express
bandwidth numbers are
bi- directional
Intel®5000X Chipset MCH
Channel2
5.3 GB/s
PCI-E x4
2 GB/s
PCI-E x4
2 GB/s
ESI
2 GB/s
Channel3
5..3 GB/s
Note: FBD Bandwidth
numbers are for FBD
4.0GHz/667MHz.
F
B
D
D
R
F
B
D
D
R
F
B
D
D
R
F
B
D
D
R
F
B
D
D
R
F
B
D
D
R
F
B
D
D
R
F
B
D
D
R
F
B
D
D
R
F
B
D
D
R
F
B
D
D
R
F
B
D
D
R
F
B
D
D
R
F
B
D
D
R
F
B
D
D
R
F
B
D
D
R
8 USB Ports
GPIO
Azalia or AC’97
3 codec
support
6 SATA Ports
1 PATA Port
Intel®631xESB/632 xESB
I/ O Controller Hub
Power
Management
Clock
Generator
PCI-E x4Bus
PCI-E x4Bus
PCI-X 133Bus
PCI32/ 33Bus
Intel® 82563EB
Network Connection
( Dual Port) PHY
RJ45
RJ45
§
SIO
Flash BIOS
Intel^® 5000X Chipset Memory Controller Hub (MCH) Datasheet
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