QG5000XSL9TH Datasheet, PDF (11/458 Pages) Intel Corporation – Intel 5000X Chipset Memory Controller Hub (MCH)

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Memory Poisoning Table................................................................................... 314
x8 Double Device Detection Characteristics......................................................... 316
SPD Addressing............................................................................................... 317
AMB Thermal Status Bit Definitions .................................................................... 323
FB_DIMM Bandwidth as a Function of Closed Loop Thermal Throttling .................... 329
Global Activation Throttling BW allocation as a function of GBLACTLM for a
16384**1344 window with MC.GTW_Mode=0 (normal) ........................................ 332
Electrical Throttle Window as a Function of DIMM Technology ................................ 333
XAPIC Data Encoding ....................................................................................... 335
Intel 5000X Chipset XAPIC Interrupt Message Routing and Delivery ...................... 336
Chipset Generated Interrupts............................................................................ 344
PCI Express Link Width Strapping Options for Port CPCI Configuration in MCH ......... 354
Options and Limitations.................................................................................... 354
PCI Express Credit Mapping for Inbound Transactions .......................................... 359
PCI Express Credit Mapping for Outbound Transactions ........................................ 360
MCH Reset Classes .......................................................................................... 363
Reset Sequences and Durations ........................................................................ 366
SMBus Transaction Field Summary .................................................................... 368
SMBus Address for Product Name Platform ......................................................... 374
SMBus Command Encoding............................................................................... 374
Status Field Encoding for SMBus Reads .............................................................. 375
MCH Supported SPD Protocols........................................................................... 379
I/O Port Registers in I/O Extender supported by Intel 5000X Chipset MCH ............. 383
Hot-Plug Signals on a Virtual Pin Port ................................................................. 384
Intel 5000X Chipset MCH Frequencies for Processors and Core ............................. 385
Intel 5000X Chipset MCH Frequencies for Memory .............................................. 385
Intel 5000X Chipset MCH Frequencies for PCI Express ......................................... 386
Clock Pins ...................................................................................................... 386
Intel 5000X chipset Error List.......................................................................... 388
TAP Signal Definitions ...................................................................................... 395
TAP Reset Actions ........................................................................................... 398
Public TAP Instructions..................................................................................... 401
Actions of Public TAP Instructions During Various TAP States................................. 402
Intel® 5000P chipset Device ID Codes ............................................................... 403
Absolute Maximum Ratings............................................................................... 405
Operating Condition Power Supply Rails ............................................................. 405
Analog and Bandgap Voltage and Current Specifications ....................................... 406
Clock DC Characteristics................................................................................... 407
FSB Interface DC Characteristics ....................................................................... 408
FB-DIMM Transmitter (Tx) Output DC Characteristics ........................................... 409
FB-DIMM Receiver (Rx) Output DC Characteristics ............................................... 409
PCI Express/ ESI Differential Transmitter (Tx) Output DC Characteristics ................ 410
PCI Express/ ESI Differential Receiver (Rx) Input DC Characteristics ...................... 410
SMBus DC Characteristics................................................................................. 411
JTAG DC Characteristics ................................................................................... 411
1.5 V CMOS DC Characteristics ......................................................................... 411
3.3 V CMOS DC Characteristics ......................................................................... 411
Intel 5000X Chipset MCH Signals (by Ball Number) .............................................. 417
Intel 5000X Chipset MCH Signals (by Signal Name) ............................................. 436
Intel® 5000X Chipset Memory Controller Hub (MCH) Datasheet
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