QG5000XSL9TH Datasheet, PDF (240/458 Pages) Intel Corporation – Intel 5000X Chipset Memory Controller Hub (MCH)

Register Description
3.9.25.2
FBD[1:0]IBPORTCTL: FB-DIMM Intel IBIST Port Control Register
This register contains bits to control the operation of the Intel IBIST DFT feature.
Device: 21
Function: 0
Offset: 280h, 180h
Bit
Attr Default
Description
31:26
RV
25
RWST
24
RW
23
RW
22
RW
21:12 RWST
11:8 ROST
7:6 RWCST
0h
0
1
0
0
000h
00h
0
Reserved
RXINVSWPMD: Rx Inversion Sweep Mode
0: Match Sweep according to the SB-to-NB_Mapping field in the TS1 training
sequence.
The default setting forces the RX inversion pointers to follow the unique
northbound inversion across the port width. It is based on a Modulo 5 of Intel
5000P Chipset MCHMAP bit setting. If e lanes Example;
If Intel 5000P Chipset MCHMAP = 0 then Lanes [4:0] are used as the reference
for checking Lanes[13:10], [9:5], and [4:0].
If Intel 5000P Chipset MCHMAP = 1 then Lanes [9:5] are used as the reference
for checking Lanes[13:10], [9:5], and [4:0].
For Intel 5000P Chipset MCH lane [13] does not exist but it does participate in
rotate-left-shift operations.
1: Enable full inversion sweep across the entire port.
When enabled the RX inversion pointers become a single entity.
Lanes [13:10] rotate left-shift completely across the width of the port. Even
though Lane[13] is a DFT lane it will be “shifted through” to make the logic
design easier.
0->1->2->3->4->5->6->7->8->9->10->11->12->13->0.
RXAUTOINVSWPEN: Auto-inversion sweep enable
This bit enable the inversion shift register to continuously rotate the pattern in
the FIBRXSHFT register.
0: Disable Auto-inversion
1: Enable Auto-inversion
Intel 5000P Chipset MCHMAP: Southbound to northbound mapping for
loopback testing
This bit indicates which set of lanes are replicated onto the northbound lanes.
0: Lower SB lanes
1: Upper SB lanes
CMMSTR: Compliance Measurement Mode
This bit forces the component into link reset then transmits the contents of the
default Intel IBIST pattern set continuously (depending on implementation) on
all Tx lanes until this bit is cleared and the IBSTR bit is cleared. If the Intel IBIST
engine is used for CMM then the standard initialization sequence is follow with
TS0, TS1 training set prior to entry into Intel IBIST.
0: Disable CMM
1: Enable CMM. This feature requires the Intel IBIST start bit to be set before the
mode is enabled.
ERRCNT: Error Counter [9:0]
Total number of errors encountered in this port. Errors are accumulated per lane.
If several errors occurred in one phit time then a binary encoded value of the
number of errors is added to the error count.
ERRLNNUM: Error Lane Number [3:0]
This points to the first lane that encountered an error. If more than one lane
reports an error in a cycle, the most significant lane number that reported the
error will be logged.
ERRSTAT: Port Error Status [1:0]
When Intel IBIST is started, status goes to 01 until first start delimiter is received
and then goes to 00 until the end or to10/11 as appropriate.
00: No error.
01: Did not receive first start delimiter.
10: Transmission error (first error).
11: Reserved.
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Intel^® 5000X Chipset Memory Controller Hub (MCH) Datasheet