QG5000XSL9TH Datasheet, PDF (257/458 Pages) Intel Corporation – Intel 5000X Chipset Memory Controller Hub (MCH)

Register Description
3.10.5 CAPPTR: Capability Pointer Register
3.10.6
3.10.7
Device:
Function:
Offset:
Version:
8
0
34h
Intel 5000P Chipset
Bit
7:0
Attr Default
Description
RO
50h
CAPPTR: Capability Pointer
This register field points to the first capability. PM structure in the DMA Engine
device.
INTL: Interrupt Line Register
The Interrupt Line register is used to communicate interrupt line routing information
between initialization code and the device driver. The Intel 5000 Series MCH does not
have a dedicated interrupt line and is not used.
Device:
Function:
Offset:
Version:
8
0
3Ch
Intel 5000P Chipset
Bit
7:0
Attr Default
Description
RWO 00h
INTL: Interrupt Line
BIOS writes the interrupt routing information to this register to indicate which input
of the interrupt controller this PCI-Express Port is connected to. Not used in the
Intel 5000 Series MCH since the PCI-Express port does not have an interrupt lines.
INTP: Interrupt Pin Register
The INTP register identifies legacy interrupts for INTA, INTB, INTC and INTD as
determined by BIOS/firmware. These are emulated over the ESI port using the
Assert_Intx commands as appropriate.
3.10.8
Device:
Function:
Offset:
Version:
8
0
3Dh
Intel 5000P Chipset
Bit
Attr
Default
Description
7:0 RWO
01h
INTP: Interrupt Pin
This field defines the type of interrupt to generate for the PCI Express port.
001: Generate INTA
010: Generate INTB
011: Generate INTC
100: Generate INTD
Others: Reserved
Power Management Capability Structure
The DMA engine integrated device within the MCH incorporates power management
capability with D0 (working) and a pseudo D3 hot/cold states (sleep) that can be
controlled independently through software. From a software perspective, the D3 states
convey information to the power controller that the device is in the sleep mode though
the physical entity inside the chipset may be fully powered. During transition¹ from D0
to D3, it will ensure that all pending DMA Channels are completed in full.
Intel^® 5000X Chipset Memory Controller Hub (MCH) Datasheet
257