QG5000XSL9TH Datasheet, PDF (141/458 Pages) Intel Corporation – Intel 5000X Chipset Memory Controller Hub (MCH)

Register Description
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
0, 2-3
0
70h
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
4-5
0
70h
Intel 5000Z Chipset
4-7
0
70h
Intel 5000P Chipset
Bit
Attr
Default
Description
8:6
RO
5
RO
4:3
RO
2:0
RO
111
EPL0AL: Endpoints L0s Acceptable Latency
This field indicates the acceptable latency that an Endpoint can withstand due
to the transition from L0s state to the L0 state.
000: Less than 64 ns
001: 64 ns to less than 128 ns
010: 128 ns to less than 256 ns
011: 256 ns to less than 512 ns
100: 512 ns to less than 1 µs
101: 1 µs to less than 2 µs
110: 2 µs to 4 µs
111: More than 4 µs
Note that Intel 5000P Chipset MCH does not support L0s implementation and
for backup, this field is set to the maximum value.
0
ETFS: Extended Tag Field Supported
This field indicates the maximum supported size of the Tag field.
0: In the Intel 5000P Chipset MCH, only 5-bit Tag field is supported
0h
PFS: Phantom Functions Supported
This field indicates the number of most significant bits of the function number
portion of Requester ID in a TLP that are logically combined with the Tag
identifier.
0: For root ports, no function number bits for phantom functions are
supported
001
MPLSS: Max Payload Size Supported
This field indicates the maximum payload size that the PCI Express port can
support for TLPs.
001: 256 B max payload size
Others - Reserved
Note that the Intel 5000P Chipset MCH only supports up to a maximum of 256
B payload (for example, writes, read completions) for each TLP and violations
will be flagged as PCI Express errors
Intel^® 5000X Chipset Memory Controller Hub (MCH) Datasheet
141