QG5000XSL9TH Datasheet, PDF (310/458 Pages) Intel Corporation – Intel 5000X Chipset Memory Controller Hub (MCH)

Functional Description
Figure 5-6 shows the positions of the next four DIMM upgrade. Like non-mirrored mode
upgrade DIMMs must be added in slot order, starting from the slot closest to the MCH.
DIMMs in a slot position must be identical with respect to size, and organization. Speed
should be matched but is not required. The MCH will adjust to the lowest speed DIMM.
DIMMs in adjacent slots need not be identical.
Figure 5-6. Mirrored Mode Next Upgrade
SLOT 3
SLOT 2
SLOT 1
SLOT 0
CHANNEL 0
CHANNEL 1
BRANCH 0
SLOT 3
SLOT 2
SLOT 1
SLOT 0
CHANNEL 2
CHANNEL 3
BRANCH 1
Memory Controller
5.3.2
Fully Buffered DIMM Technology and Organization
Fully Buffered DIMM technology was developed to address the higher performance
needs of server and workstation platforms. FB-DIMM addresses the dual needs for
higher bandwidth and larger memory sizes.
FB-DIMM memory DIMMs contain an Advanced Memory Buffer (AMB) device that
serves as an interface between the point to point FB-DIMM Channel links and the DDR2
DRAM devices. Each AMB is capable of buffering up to two ranks of DRAM devices. Each
AMB supports two complete FB-DIMM channel interfaces. The first FB-DIMM interface is
the incoming interface between the AMB and its proceeding device. The second
interface is the outgoing interface and is between the AMB and its succeeding device.
The point to point FB-DIMM links are terminated by the last AMB in a chain. The
outgoing interface of the last AMB requires no external termination.
There are three major components of the FB-DIMM channel interface:
• 14 Differential Northbound Signal pairs
• 10 Differential Southbound Signal pairs
• 1 Differential Clock Signal pair
Figure 5-7 depicts a single FB-DIMM channel with these three signal groups.
310
Intel^® 5000X Chipset Memory Controller Hub (MCH) Datasheet