QG5000XSL9TH Datasheet, PDF (263/458 Pages) Intel Corporation – Intel 5000X Chipset Memory Controller Hub (MCH)

Register Description
Device:
Function:
Offset:
Version:
8
0
60h
Intel 5000P Chipset
Bit
10:8
7:0
Attr Default
Description
RW
0h DM: Delivery Mode
000: Fixed
001: Lowest Priority
010: SMI/HMI
011: Reserved
100: NMI
101: INIT
110: Reserved
111: ExtINT
RW
0h IV: Interrupt Vector
The interrupt vector as programmed by BIOS/Software will be used by the Intel
5000P Chipset MCH to provide context sensitive interrupt information for different
events such as DMA Errors, DMA completions that require attention from the
processor. See Table 3-50 for IV handling for DMA.
Table 3-50. IV Vector Table for DMA Errors and Interrupts
Number of Messages
enabled by Software
(MMEN)
Events
IV[7:0]
1
All
xxxxxxxx¹
(DMA completions/errors)
Notes:
1. The term “xxxxxx” in the Interrupt vector denotes that software/BIOS initializes them
and the MCH will not modify any of the “x” bits since it handles only 1 message vector
that is common to all events
3.10.14 PEXCAPID: PCI Express Capability ID Register
Device:
Function:
Offset:
Version:
8
0
6Ch
Intel 5000P Chipset
Bit
7:0
Attr Default
Description
RO
10h
CAPID: PCI Express Capability ID
This code denotes the standard PCI Express capability.
3.10.15 PEXNPTR: PCI Express Next Pointer Register
Device:
Function:
Offset:
Version:
8
0
6Dh
Intel 5000P Chipset
Bit
7:0
Attr Default
Description
RO
00h
NXTPTR: PCI Express Next Pointer
The PCI Express capability structure is the last capability in the linked list and set to
NULL.
Intel^® 5000X Chipset Memory Controller Hub (MCH) Datasheet
263