QG5000XSL9TH Datasheet, PDF (180/458 Pages) Intel Corporation – Intel 5000X Chipset Memory Controller Hub (MCH)

Register Description
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
0, 2-3
0
160h
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
4-5
0
160h
Intel 5000Z Chipset
Device:
Function:
Offset:
Version:
4-7
0
160h
Intel 5000P Chipset
Bit
31:18
17
16
15
14
13
12
11
10
Attr
RV
RWST
RWCST
RWCST
RWCST
RWCST
RWCST
RWCST
RWCST
9
RWCST
8
RWCST
7
RWCST
6
RWCST
5
RWCST
4
RWCST
3
RWCST
2
RWCST
1
RWCST
0
RWCST
Default
0h
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Description
Reserved
Next_NFAT_Corr_Err_IO19: Surprise Link Down
Next_NFAT_COR_Err_IO17: PEX - Received Correctable Error Message
Next_NFAT_COR_Err_IO16: PEX - Replay Timer Timeout (correctable)
Next_NFAT_COR_Err_IO15: PEX - Replay_Num Rollover (correctable)
Next_NFAT_COR_Err_IO14: PEX - BAD DLLP Error (correctable)
Next_NFAT_COR_Err_IO13: PEX - Bad TLP Error (correctable)
Next_NFAT_COR_Err_IO12: PEX - Receiver Error (correctable)
Next_NFAT_COR_Err_IO11: PEX - Received Non Fatal (uncorrectable)
Error Message
Next_NFAT_COR_Err_IO10: PEX - Receive Buffer Overflow Error
(uncorrectable)
Next_NFAT_COR_Err_IO9: PEX -Malformed TLP (uncorrectable)
Next_NFAT_COR_Err_IO8: PEX - Unexpected Completion Error
(uncorrectable)
Next_NFAT_COR_Err_IO7: PEX - Completer Abort (uncorrectable)
Next_NFAT_COR_Err_IO6: PEX - Completion Timeout (uncorrectable)
Next_NFAT_COR_Err_IO5: PEX - Flow Control Protocol Error
(uncorrectable)
Next_NFAT_COR_Err_IO4: PEX - Poisoned TLP (uncorrectable)
Next_NFAT_COR_Err_IO3: PEX - Training Error (uncorrectable)
This field should not be used for setting Training error severity due to a
recent PCI-SIG ECN (Jan 22, 04) to remove training error. Hardware
behavior is undefined.
Next_NFAT_COR_Err_IO2: PEX - Received Unsupported Request
(uncorrectable)
Next_NFAT_COR_Err_IO0: PEX - Data Link Layer Protocol Error
(uncorrectable)
3.8.12.28 PEX_UNIT_FERR[7:2, 0] - PCI Express First Unit Error Register
This register records the occurrence of the first unit errors that are specific to this PCI
Express port caused by external activities. For example, VPP error due to a
malfunctioning port on the SMBUS that did not receive acknowledge due to a PCI
Express hot-plug event. The unit errors are sent to the Coherency Engine to classify as
to which port cluster it came from ports 2-3 or ports 4-7 and the errors are recorded in
Coherency Engine and appropriate interrupts generated through ERR pins.
180
Intel^® 5000X Chipset Memory Controller Hub (MCH) Datasheet