QG5000XSL9TH Datasheet, PDF (376/458 Pages) Intel Corporation – Intel 5000X Chipset Memory Controller Hub (MCH)

Functional Description
Figure 5-38. SMBus Configuration Read (Word Writes / Word Reads, PEC Enabled)
S
11X0_XXX
W A Cmd = 10010001 A
Bus Number
A
Device/Function
A
S
11X0_XXX
W A Cmd = 01010001 A Register Number[15:8] A Register Number[7:0] A
S
11X0_XXX
W A Cmd = 10010001 A
Sr
11X0_XXX
RA
Status
A
Data[31:24]
A
PEC
NP
S
11X0_XXX
W A Cmd = 00010001 A
Sr
11X0_XXX
RA
Data[23:16]
A
Data[15:8]
A
PEC
NP
S
11X0_XXX
W A Cmd = 01010000 A
Sr
11X0_XXX
RA
Data[7:0]
A
PEC
NP
PEC
PEC
AP
CLOCK
STRETCH
AP
The following example uses byte reads.
Figure 5-39. SMBus Configuration Read (Write Bytes / Read Bytes, PEC Enabled)
S
11X0_XXX
W A Cmd = 10010000 A
Bus Number
A
S
11X0_XXX
W A Cmd = 00010000 A
Device/Function
A
S
11X0_XXX
W A Cmd = 00010000 A
Register[15:8]
A
S
11X0_XXX
W A Cmd = 01010000 A
Register[7:0]
A
PEC
PEC
PEC
PEC
AP
AP
AP
CLOCK STRETCH A P
S
11X0_XXX
W A Cmd = 10010000 A
Sr
11X0_XXX
RA
Status
A
S
11X0_XXX
W A Cmd = 00010000 A
Sr
11X0_XXX
RA
Data[31:24]
A
S
11X0_XXX
W A Cmd = 00010000 A
Sr
11X0_XXX
RA
Data[23:16]
A
S
11X0_XXX
W A Cmd = 00010000 A
Sr
11X0_XXX
RA
Data[15:8]
A
S
11X0_XXX
W A Cmd = 01010000 A
Sr
11X0_XXX
RA
Data[7:0]
A
PEC
PEC
PEC
PEC
PEC
NP
NP
NP
NP
NP
5.16.4.3 Configuration Register Write Protocol
Configuration writes are accomplished through a series of SMBus writes. As with
configuration reads, a write sequence is first used to initialize the Bus Number, Device,
Function, and Register Number for the configuration access. The writing of this
information can be accomplished through any combination of the supported SMBus
write commands (block, word or byte).
Examples of configuration writes are illustrated below. For the definition of the diagram
conventions below, refer to the SMBus Specification, Revision 2.0.
Figure 5-40. SMBus Configuration Write (Block Write, PEC Enabled)
S 11X0_XXX WA Cmd = 11011110 A Byte Count = 8 A Bus Number A Device/Function A Reg Number[15:8] A Reg Number [7:0] A Data[31:24]
A Data[23:16] A Data[16:8] A
Data[7:0]
A
PEC
CLOCK
STRETCH
AP
376
Intel^® 5000X Chipset Memory Controller Hub (MCH) Datasheet