QG5000XSL9TH Datasheet, PDF (150/458 Pages) Intel Corporation – Intel 5000X Chipset Memory Controller Hub (MCH)

Register Description
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
0, 2-3
0
7Eh
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
4-5
0
7Eh
Intel 5000Z Chipset
Device:
Function:
Offset:
Version:
4-7
0
7Eh
Intel 5000P Chipset
Bit
Attr
Default
Description
11
RO
0
LNKTRG: Link Training
This field indicates the status of an ongoing link training session in the current
PCI Express port and is controlled by the Hardware.
0: indicates that the LTSSM is neither in “Configuration” nor “Recovery” states.
1: indicates Link training in progress (Physical Layer LTSSM is in
Configuration or Recovery state or the RLNK (retrain link) was set in
Section 3.8.11.7 but training has not yet begun.
Also refer to the BCTRL.SBUSRESET for details on how the Link training bit can
be used for sensing Hot-reset states.
10
RO
0
TERR: Training Error
This field indicates the occurrence of a Link training error.
0: indicates no Link training error occurred.
1: indicates Link training error occurred.
9:4
RO
000100 NLNKWD: Negotiated Link Width¹
This field indicates the negotiated width of the given PCI Express link after
training is completed.
Only x1, x4, x8, and x16 link width negotiations are possible in the Intel
5000P Chipset MCH. Refer to Table 3-36 for the port and link width
assignment after training is completed.
3:0
RO
1h
LNKSPD: Link Speed
This field indicates the negotiated Link speed of the given PCI Express Link:
0001- 2.5 Gb/s PCI Express link
Others - Reserved
Notes:
1. The NLNKWD field is set to a default value corresponding to x4 internally within the Intel 5000P Chipset MCH.
Note that this field is a don’t care until training is completed for the link. Software should not use this field to
determine whether a link is up (enabled) or not.
Table 3-36. Negotiated Link Width For Different PCI Express Ports After Training
Device/Port
Negotiated Link Width
2,3,4,5,6,7
x1
0,2,3,4,5,6,7
x4
2,4,6
x8
4
x16
Notes:
1. Ports 3, 5, and 7 report 000000 as appropriate.
2. Ports 5, 6, and 7 report 000000 as appropriate.
Value
000001
000100
001000¹
010000²
3.8.11.9 PEXSLOTCAP[7:2, 0] - PCI Express Slot Capabilities Register
The Slot Capabilities register identifies the PCI Express specific slot capabilities.
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Intel^® 5000X Chipset Memory Controller Hub (MCH) Datasheet