QG5000XSL9TH Datasheet, PDF (102/458 Pages) Intel Corporation – Intel 5000X Chipset Memory Controller Hub (MCH)

Figure 3-4. PCI Express Configuration Space
0xFFF
Register Description
Intel® 5000P
Chipset Advanced Error
Reporting
PCI-Express Advanced
Error Reporting
0x140
0x100
PCI-Express Capability
MSI Capability
PM Capability
3.8.8
CAP_PTR
P2P
0x40
0x00
Figure 3-3 shows the configuration register offset addresses for each of the PCI
Express ports as defined in the PCI Express Base Specification, Revision 1.0a. It is also
compatible with the standard PCI 2.3 capability structure and comprises of a linked list
where each capability has a pointer to the next capability in the list. For PCI Express
extended capabilities, the first structure is required to start at 0x100 offset.
PCI Express Header
The following registers define the standard PCI 2.3 compatible and extended PCI
Express configuration space for each of the PCI Express x4 links in the MCH. Unless
otherwise specified, the registers are enumerated as a vector [2:7] mapping to each of
the six PCI Express ports uniquely while the ESI port is referred by index 0.
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Intel^® 5000X Chipset Memory Controller Hub (MCH) Datasheet