QG5000XSL9TH Datasheet, PDF (50/458 Pages) Intel Corporation – Intel 5000X Chipset Memory Controller Hub (MCH)

Register Description
3.4.2
Special Device and Function Routing
All devices in the Intel® 5000X chipset MCH reside on Bus 0. The following table
describes the devices and functions that the MCH implements or routes specially. The
DIMM component designator consists of a three-digit code: the first digit is the branch,
the second digit is the channel on the branch, and the third digit is the DIMM (FB-DIMM
command “DS” field) on the channel.
Table 3-3. Functions Specially Handled by the MCH
Component
Register Group
MCH
MCH
MCH
MCH
MCH
MCH
MCH
MCH
MCH
MCH
MCH
DIMM
PCI Express Port 2
PCI Express Port 3
PCI Express Port 4
PCI Express Port 5
PCI Express Port 6
PCI Express Port 7
DMA Engine
DMA Engine MMIO Space
Memory Map, Error Flag/Mask,
RAS, Channel Control for FB-
DIMM Branch 0
Memory Map, Error Flag/Mask,
RAS, Channel Control for FB-
DIMM Branch 1
Processor Bus, Boot, Interrupt,
System Address
AMB Memory Mapped registers
DID
25E2h
25E3h
25E4h
25E5h
25E6h
25E7h
1A38h
N/A
25F5h
25F6h
25F0h
N/A
MCH
MCH
MCH
MCH
MCH
MCH
Address Mapping, Memory
Control, Error Logs
FSB Error Registers
PCI Express Port 2-3
PCI Express Port 4-5
PCI Express Port 6-7
PCI Express Port 4-7
25F0h
25F0h
25F7h
25F8h
25F9h
25FAh
Device
Functio
n
Comment
2
0
3
0
4
0
5
0
6
0
7
0
8
0
8
1
21
0
Depending on what is
connected to these
ports, some may not be
accessible.
New device mapping for
DMA Engine
Debug and DFT in
higher address offsets.
22
0
Debug and DFT in
higher address offsets.
16
0
9
0
16
1
16
2
2
0
4
0
6
0
4
0
Debug and DFT in
higher address offsets.
Route out to AMB per
AMBSELECT register
only for JTAG/SMBus.
Debug and DFT in
higher address offsets.
x8 mode. Only port 2 is
active
x8 mode. Only port 4 is
active
x8 mode. Only port 6 is
active
x16 mode. Only port 4
is active
To comply with the PCI specification, accesses to non-existent functions, registers, and
bits will be master aborted. This behavior is defined in the following table:
50
Intel^® 5000X Chipset Memory Controller Hub (MCH) Datasheet