QG5000XSL9TH Datasheet, PDF (261/458 Pages) Intel Corporation – Intel 5000X Chipset Memory Controller Hub (MCH)

Register Description
Figure 3-7. Intel 5000P Chipset DMA Error/Channel Completion Interrupt Handling Flow
DMA errors/completion
interrupts
Y
(MSICTRL[x].
MSIEN == 1)
N
(PEXCTRL[x]
Y
MSICBEN == 1)?
N
MSIDR
PEXCMD[x].INTx
Disable == 1?
Y
N Intel® 5000P Chipset
Sends assert_INTx
message via DMI
per INTP
Intel® 5000P Chipset
Sends deassert_INTx
message via DMI
per INTP when
INTRCTRL.intp is
reset (wired-OR)
Will send only 1
MSI For both DMA
interrupts and
Channel completions
MSIEN
1
1
0
0
MSICBEN
1
0
x
x
INTx Disable
x
x
0
1
Output
MSI
--
assert_intx
--
Intel^® 5000X Chipset Memory Controller Hub (MCH) Datasheet
261