QG5000XSL9TH Datasheet, PDF (241/458 Pages) Intel Corporation – Intel 5000X Chipset Memory Controller Hub (MCH)

Register Description
Device: 21
Function: 0
Offset: 280h, 180h
Bit
Attr Default
Description
5
RW
4
RW
3
RW
2
RWCST
1
RWST
0
RWST
TXAUTOINVSWPEN: Auto-inversion sweep enable
This bit enable the inversion shift register to continuously rotate the pattern in
1
the FIBTXSHFT register.
0: Disable Auto-inversion
1: Enable Auto-inversion
STOPONERR: Stop Intel IBIST on Error
1
0: Do not stop on error, only update error counter
1: Stop on error
LOOPCON: Loop continuously
Enable IBIST operations to loop continuously. The Intel IBIST pattern generator
executes the each pattern loop for the counts specified in the bit fields but the
0
overall loop runs continuously. This bit should be protected (gated) by the
component’s security mechanisms.
0: No continuous operation
1: Loop continuously
IBDONE: Intel IBIST done flag
0
0: Not done
1: Done
MSTRMD: Master Mode Enable
When this bit is set the next TS1 training set that has the loopback bit set will
cause the transmitter to operate as a master. Even though the Intel IBIST is in
1
the loopback state it is not in loopback.
0: Disable Master mode. This component will not enter into master when a TS1
training set with loopback bit set.
1: Enable Master Mode on the next TS1 training with loopback bit set
IBSTR: Intel IBIST Start
When set, it enables receiver logic to look for start delimiters during TS1 training
set. If the MSTRMD bit is set, the start bit enables the transmit state machine to
start transmitting patterns during the TS1 training set. The receiver is enable in
both cases.
0
For master-slave mode, the pattern will be looped back as defined in the FB-
DIMM spec. In master-master mode, the Intel IBIST controller will originate
patterns and also check the incoming pattern for errors.
0: Stop Intel IBIST transmitter
1: Start Intel IBIST transmitter
Intel^® 5000X Chipset Memory Controller Hub (MCH) Datasheet
241