QG5000XSL9TH Datasheet, PDF (166/458 Pages) Intel Corporation – Intel 5000X Chipset Memory Controller Hub (MCH)

Register Description
3.8.12.8
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
2-3
0
10Ch
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
4-5
0
10Ch
Intel 5000Z Chipset
Device:
Function:
Offset:
Version:
4-7
0
10Ch
Intel 5000P Chipset
Bit
14
13
12
11:6
5
4
Attr
RWST
RWST
RWST
RV
RWST
RWST
3:1
RV
0
RWST
Default
0
1
0
0h
0
1
000
1
Description
IO6Severity: Completion Time-out Severity
IO5Severity: Flow Control Protocol Error Severity
IO4Severity: Poisoned TLP Severity
Reserved
IO19Severity: Surprise Link Down Severity
IO0Severity: Data Link Protocol Error Severity
(See Figure 3-17 in PCI Express Base Specification, Revision 1.0a)
Reserved
IO3Severity:Training Error Severity
This field should not be used for setting Training error severity due to a
recent PCI Express Base Specification, Revision 1.0a Errata Dec 2003 to
remove training error. Hardware behavior is undefined.
CORERRSTS[7:2, 0] - Correctable Error Status
This register identifies which unmasked correctable error has been detected. The error
is directed to the respective device correctable error bit in the PEX_NF_COR_FERR,
PEX_NF_COR_NERR registers (If the error is unmasked in the CORERRMSK register
defined in Section 3.8.12.9). These registers are discussed starting from
Section 3.8.12.25.
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
0, 2-3
0
110h
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
4-5
0
110h
Intel 5000Z Chipset
Device:
Function:
Offset:
Version:
4-7
0
110h
Intel 5000P Chipset
Bit
31:13
12
11:9
8
Attr
RV
RWCST
RV
RWCST
Default
0h
0
0h
0
Description
Reserved
IO16Err: Replay Timer Time-out Status
Reserved
IO15Err: Replay_Num Rollover Status
166
Intel^® 5000X Chipset Memory Controller Hub (MCH) Datasheet