QG5000XSL9TH Datasheet, PDF (187/458 Pages) Intel Corporation – Intel 5000X Chipset Memory Controller Hub (MCH)

Register Description
3.8.13.12 ERR2_FSB[1:0]: FSB Error 2 Mask Register
This register enables the signaling of Err[2] when an error flag is set. Note that one and
only one error signal should be enabled ERR2_FSB, ERR1_FSB, ERR0_FSB, and
MCERR_FSB for each of the corresponding bits.
.
Device:
Function:
Offset:
Version:
16
0
498h, 198h
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Bit
15:9
8
7
6
5
4
3
2
1
0
Attr
RV
RWST
RWST
RWST
RWST
RV
RV
RV
RWST
RWST
Default
0h
1
1
1
1
0
0h
0h
1
1
Description
Reserved
F9Msk: FSB Protocol Error
F8Msk: B-INIT
F7Msk: Detected MCERR
F6Msk: Data Parity Error
Reserved
Reserved
Reserved
F2Msk: Unsupported Processor Bus Transaction
F1Msk: Request/Address Parity Error
3.8.13.13 ERR1_FSB[1:0]: FSB Error 1 Mask Register
This register enables the signaling of Err[1] when an error flag is set. Note that one and
only one error signal should be enabled ERR2_FSB, ERR1_FSB, ERR0_FSB, and
MCERR_FSB for each of the corresponding bits.
Device:
Function:
Offset:
Version:
16
0
496h, 196h
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Bit
15:9
8
7
6
5
4
3
2
1
0
Attr
RV
RWST
RWST
RWST
RWST
RV
RV
RV
RWST
RWST
Default
0h
1
1
1
1
0h
0h
0h
1
1
Description
Reserved
F9Msk: FSB Protocol Error
F8Msk: B-INIT
F7Msk: Detected MCERR
F6Msk: Data Parity Error
Reserved
Reserved
Reserved
F2Msk: Unsupported Processor Bus Transaction
F1Msk: Request/Address Parity Error
3.8.13.14 ERR0_FSB[1:0]: FSB Error 0 Mask Register
This register enables the signaling of Err[0] when an error flag is set. Note that one and
only one error signal should be enabled ERR2_FSB, ERR1_FSB, ERR0_FSB, and
MCERR_FSB for each of the corresponding bits.
Intel^® 5000X Chipset Memory Controller Hub (MCH) Datasheet
187