QG5000XSL9TH Datasheet, PDF (139/458 Pages) Intel Corporation – Intel 5000X Chipset Memory Controller Hub (MCH)

Register Description
3.8.11.3
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
0, 2-3
0
6Eh
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
4-5
0
6Eh
Intel 5000Z Chipset
4-7
0
6Eh
Intel 5000P Chipset
Bit
13:9
Attr
RO
8
if
(port
7-2)
{RW
O}
elsif
(port
0)
{RO}
endif
7:4
RO
3:0
RO
Default
00h
0
0100
0001
Description
IMN: Interrupt Message Number
This field indicates the interrupt message number that is generated from the
PCI Express port. When there are more than one MSI interrupt Number, this
register field is required to contain the offset between the base Message Data
and the MSI Message that is generated when the status bits in the slot status
register or root port status registers are set. The chipset is required to update
the field if the number of MSI messages changes.
SLOT_Impl: Slot Implemented
1: indicates that the PCI Express link associated with the port is connected to a
slot.
0: indicates no slot is connected to this port.
This register bit is of type “write once” and is controlled by BIOS/special
initialization firmware.
For the DMI port, this value should always be 0b since it is not hot-pluggable
and it is required for boot.
Rest of the PCI_Express ports which are slotted/hot-pluggable, BIOS or
Software can set this field to enable the slots.
DPT: Device/Port Type
This field identifies the type of device. It is set to 0100 as defined in the spec
since the PCI Express port is a “root port” in the Intel 5000P Chipset MCH.
VERS: Capability Version
This field identifies the version of the PCI Express capability structure. Set to
0001 by PCI SIG.
PEXDEVCAP[7:2, 0] - PCI Express Device Capabilities Register
The PCI Express Device Capabilities register identifies device specific information for
the port.
Intel^® 5000X Chipset Memory Controller Hub (MCH) Datasheet
139