QG5000XSL9TH Datasheet, PDF (48/458 Pages) Intel Corporation – Intel 5000X Chipset Memory Controller Hub (MCH)

Register Description
3.3.3 Primary PCI and Downstream Configuration Mechanism
If the Bus Number in the CONFIG_ADDRESS is non-zero, the MCH will generate a Type
1 PCI configuration cycle. A[1:0] of the ESI request packet for the Type 1 configuration
cycle will be 01. Bits 31:2 of the CONFIG_ADDRESS register will be translated to the
A[31:2] field of the ESI request packet of the configuration cycle as shown in
Figure 3-2. This configuration cycle will be sent over the ESI to Intel 631xESB/632xESB
I/O Controller Hub.
If the cycle is forwarded to the Intel 631xESB/632xESB I/O Controller Hub via ESI, the
Intel 631xESB/632xESB I/O Controller Hub compares the non-zero Bus Number with
the Secondary Bus Number and Subordinate Bus Number Registers of its PCI-to-PCI
bridges to determine if the configuration cycle is meant for primary PCI bus, one of the
Intel 631xESB/632xESB I/O Controller Hub’s PCI Express ports, or a downstream PCI
bus.
Figure 3-2. Type 1 Configuration Address to PCI Address Mapping
CONFIG_ADDRESS
33
10
22
43
16 15
11
1
0
87
21 0
1 Reserved Bus Number Device Number Function Number Reg. Index X X
3.4
PCI Address
AD[31:0]
0
Bus
Number
Device
Number
Function Number
Reg.
Index
01
31
22
43
16 15
11
10
87
21 0
Device Mapping
Each component in a Intel® 5000X chipset system is uniquely identified by a PCI bus
address consisting of; Bus Number, Device Number and Function Number. Device
configuration is based on the PCI Type 0 configuration conventions. All PCI devices
within a Intel® 5000X chipset platform must support Type 0 configuration accesses. All
MCH registers in the Intel® 5000X chipset MCH appear on Bus #0.
All Intel® 5000X chipset MCH configuration registers reside in the configuration space
defined by Bus, Device, Function, Register address. Some registers do not appear in all
portions of this space and some mechanisms do not access all portions of this space. In
general the configuration space is sparsely populated. The following table defines
where the various fields of configuration register addresses appear. Each row defines a
different access mechanism, register, interface, or decoder. Each column defines a
different field of the configuration address.
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Intel^® 5000X Chipset Memory Controller Hub (MCH) Datasheet