QG5000XSL9TH Datasheet, PDF (294/458 Pages) Intel Corporation – Intel 5000X Chipset Memory Controller Hub (MCH)

System Address Map
For all table entries where an access is forwarded to ESI to be master aborted, if an
access comes from ESI, the Intel 5000X chipset MCHESI may master abort a
transaction without forwarding it back to the ESI.
Table 4-10. Address Disposition for Inbound Transactions (Sheet 1 of 2)
Address
Range
Conditions
Intel 5000P Chipset Behavior
DOS
0 to 09FFFFh
Coherent Request to Main Memory.
Route to main memory according to Intel 5000P
Chipset MCH.MIR registers. Apply Coherence Protocol.
SMM/VGA
0A0000h to 0BFFFFh,
and VGAEN=0
Send to ESI to be master aborted. Set
EXSMRAMC.E_SMERR
C, D, E, and F
BIOS segments
0A0000h to 0BFFFFh
and VGAEN=1
0C0000h to 0FFFFFh and PAM=11²
Non-coherent read/write request to the decoded PCI
Express or to ESI based on BCTRL¹
Non-coherent request to main memory. (Coherency
does not need to be guaranteed. Coherency protocol
can be followed if it simplifies implementation.) Route
to appropriate FB-DIMM according to Intel 5000P
Chipset MCH.MIR registers.
Low/Medium 10_0000 <= Addr < ESMMTOP -
Memory
TSEG_SZ
Coherent Request to Main Memory. Route to main
memory according to Intel 5000P Chipset MCH.MIR
registers. Apply Coherence Protocol.
Extended
ESMMTOP -TSEG_SZ <= Addr <
SMRAM Space ESMMTOP
Send to system memory if G_SMRAME = 0 or
(G_SMRAME = 1 and T_EN = 0); otherwise Send to
ESI to be master aborted. Set EXSMRAMC.E_SMERR
bit
Low MMIO
TOLM <= Addr < FE00_0000 and Request to PCI Express based on <MBASE/MLIMIT and
falls into a legal BASE/LIMIT range PMBASE/PMLIMIT> registers.
TOLM <= Addr < FE00_0000 and
not in a legal BASE/LIMIT range
Send to ESI to be master aborted.
PCI Express
MMCFG
HECBASE <= Addr <
HECBASE+256MB
Inbound MMCFG access is not allowed and will be
aborted.
Intel 5000X FE00_0000h to FEBF_FFFFh AND
chipset specific valid Intel 5000P Chipset memory
mapped register address
Inbound MMCFG access is not allowed and will be
aborted.
FE00_0000h to FEBF_FFFFh AND
NOT a valid Intel 5000P Chipset
memory mapped register address
Send to ESI to be master aborted.
I/O APIC
registers
FEC0_0000 to FEC8_FFFFh
Non-coherent request to PCI Express or ESI based on
Table 4-4
Intel 631xESB/
632xESB I/O
Controller Hub
/ Intel
631xESB/
632xESB I/O
Controller Hub
timers
FEC9_0000h to FED1_FFFF
Issue request to ESI.
High SMM
FEDA_0000h to FEDB_FFFF
Send to ESI to be master aborted. Set
EXSMRAMC.E_SMERR bit
Interrupt
Inbound write to FEE0_0000h -
FEEF_FFFFh
Route to appropriate FSB(s). See Interrupt Chapter for
details on interrupt routing.
memory transaction (other than
write) to FEE0_0000h -
FEEF_FFFFh
Send to ESI to be master aborted.
Firmware
FF00_0000h to FFFF_FFFFh
Master abort
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Intel^® 5000X Chipset Memory Controller Hub (MCH) Datasheet