QG5000XSL9TH Datasheet, PDF (114/458 Pages) Intel Corporation – Intel 5000X Chipset Memory Controller Hub (MCH)

Register Description
3.8.8.16
Notes:
1. In general, the DPE field is the superset of the MDPERR from a virtual PCI-PCI bridge perspective
but there may be cases where a PCISTS[8].MDPERR may not be logged in the PCISTS[15].DPE
field in the Intel 5000P Chipset MCH on the primary side.
MBASE[7:2] - Memory Base
The Memory Base and Memory Limit registers define a memory mapped I/O non-
prefetchable address range (32-bit addresses) and the MCH directs accesses in this
range to the PCI Express port based on the following formula:
MEMORY_BASE <= A[31:20] <= MEMORY_LIMIT
The upper 12 bits of both the Memory Base and Memory Limit registers are read/write
and corresponds to the upper 12 address bits, AD[31:20], of 32-bit addresses. For the
purpose of address decoding, the bridge assumes that the lower 20 address bits,
AD[19:0], of the memory base address are zero. Similarly, the bridge assumes that the
lower 20 address bits, AD[19:0], of the memory limit address (not implemented in the
Memory Limit register) are FFFFFh. Thus, the bottom of the defined memory address
range will be aligned to a 1 MB boundary and the top of the defined memory address
range will be one less than a 1 MB boundary. Refer to Section 4.3.9, Section 4.4.2 and
Section 4.4.3 in the Intel 5000P Chipset programmer’s guide for further details on
address mapping.
3.8.8.17
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
2-3
0
20h
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
4-5
0
20h
Intel 5000Z Chipset
4-7
0
20h
Intel 5000P Chipset
Bit
15:4
Attr
RW
3:0
RO
Default
0h
0h
Description
MBASE: Memory Base Address
Corresponds to A[31:20] of the memory address on the PCI Express port.
Reserved. (by PCI SIG)
MLIM[7:2]: Memory Limit
This register controls the processor to PCI Express non-prefetchable memory access
routing based on the following formula as described above:
MEMORY_BASE <= A[31:20] <= MEMORY_LIMIT
The upper 12 bits of the register are read/write and correspond to the upper 12
address bits A[31:20] of the 32 bit address. The bottom 4 bits of this register are read-
only and return zeroes when read. This register must be initialized by the configuration
software. For the purpose of address decode address bits A[19:0] are assumed to be
FFFFFh.
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Intel^® 5000X Chipset Memory Controller Hub (MCH) Datasheet