QG5000XSL9TH Datasheet, PDF (94/458 Pages) Intel Corporation – Intel 5000X Chipset Memory Controller Hub (MCH)

Register Description
3.8.4.2
.
3.8.5
3.8.5.1
Device:
Function:
Offset:
Version:
16
0
6Eh
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Bit
11:8
Attr
RW
7:4
RW
3:0
RW
Default
0h
0h
0h
Description
BUCKET2: First priority number not in BUCKET0, BUCKET1, or
BUCKET2.
Must be programmed with a larger value than BUCKET1. A suggested value
is Ch.
BUCKET1: First priority number not in BUCKET0 or BUCKET1.
Must be programmed with a larger value than BUCKET0. A suggested
value is 8h.
BUCKET0: First priority number not in BUCKET0. A suggested value is 0h.
REDIRBUCKETS - Redirection Bucket Number Register
This register allows software to read the current hardware bucket number assigned to
each XTPR register.
Device:
Function:
Offset:
Version:
16
0
68h
Intel 5000P Chipset, Intel 5000V Chipset
Bit
31:30
29:28
27:26
25:24
23:22
21:20
19:18
17:16
15:14
13:12
11:10
9:8
7:6
5:4
3:2
1:0
Attr
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Default
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Description
BUCKET15: Redirection bucket number for XTPR[15].
BUCKET14: Redirection bucket number for XTPR[14].
BUCKET13: Redirection bucket number for XTPR[13].
BUCKET12: Redirection bucket number for XTPR[12].
BUCKET11: Redirection bucket number for XTPR[11].
BUCKET10: Redirection bucket number for XTPR[10].
BUCKET9: Redirection bucket number for XTPR[9].
BUCKET8: Redirection bucket number for XTPR[8].
BUCKET7: Redirection bucket number for XTPR[7].
BUCKET6: Redirection bucket number for XTPR[6].
BUCKET5: Redirection bucket number for XTPR[5].
BUCKET4: Redirection bucket number for XTPR[4].
BUCKET3: Redirection bucket number for XTPR[3].
BUCKET2: Redirection bucket number for XTPR[2].
BUCKET1: Redirection bucket number for XTPR[1].
BUCKET0: Redirection bucket number for XTPR[0].
Boot and Reset Registers
SYRE - System Reset Register
This register controls MCH reset behavior. Any resets produced by a write to this
register must be delayed until the configuration write is completed on the initiating
interface (PCI Express, ESI, processor bus, SMBus, JTAG).
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Intel^® 5000X Chipset Memory Controller Hub (MCH) Datasheet