QG5000XSL9TH Datasheet, PDF (146/458 Pages) Intel Corporation – Intel 5000X Chipset Memory Controller Hub (MCH)

Register Description
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
0, 2-3
0
78h
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
4-5
0
78h
Intel 5000Z Chipset
Device:
Function:
Offset:
Version:
4-7
0
78h
Intel 5000P Chipset
Bit
Attr
Default
Description
31:24
23:18
17:15
14:12
RWO
RV
RO
RO
if (port 0)
{0h} elsif
(port 2)
{02h} elsif
(port 3)
{03h} elsif
(port 4)
{04h} elsif
(port 5)
{05h} elsif
(port 6)
{06h} elsif
(port 7)
{07h} endif
0h
7h
7h
PN: Port Number
This field indicates the PCI Express port number for the link and is initialized
by software/BIOS. This will correspond to the device number for each port.
port 0- device number of 0 (ESI)
port 2 - device number of 2
port 3 - device number of 3
port 4 - device number of 4
port 5- device number of 5
port 6- device number of 6
port 7- device number of 7
Reserved.
L1EL: L1 Exit Latency
This field indicates the L1 exit latency for the given PCI Express port. It
indicates the length of time this port requires to complete transition from L1
to L0.
000: Less than 1µs
001: 1 µs to less than 2 µs
010: 2 µs to less than 4 µs
011: 4 µs to less than 8 µs
100: 8 µs to less than 16 µs
101: 16 µs to less than 32 µs
110: 32 µs to 64 µs
111: More than 64us
The Intel 5000P Chipset MCH does not support L1 acceptable latency and is
set to the maximum value for safety
L0sEL: L0s Exit Latency
This field indicates the L0s exit latency (i.e L0s to L0) for the PCI Express
port.
000: Less than 64 ns
001: 64 ns to less than 128 ns
010: 128 ns to less than 256 ns
011: 256 ns to less than 512 ns
100: 512 ns to less than 1 µs
101: 1 µs to less than 2 µs
110: 2 µs to 4 µs
111: More than 4 µs
Note that Intel 5000P Chipset MCH does not support L0s exit latency
implementation and for safety, this field is set to the maximum value.
146
Intel^® 5000X Chipset Memory Controller Hub (MCH) Datasheet