QG5000XSL9TH Datasheet, PDF (77/458 Pages) Intel Corporation – Intel 5000X Chipset Memory Controller Hub (MCH)

Register Description
The CRID is not a directly addressable PCI register. The CRID value is reflected through
the RID register when appropriately addressed.The 4 bits of the CRID are reflected as
the two least significant bits of the major and minor revision field respectively. See
Figure 3-3.
Figure 3-3. Intel 5000P Chipset MCH implementation of SRID and CRID Registers
76543210
Major Rev Id Minor Rev Id
3.8.1.4
CCR - Class Code Register
This register contains the Class Code for the device. Writes to this register have
no effect.
Device¹:0, 2-3, 9
Function: 0
Offset:
09h
Version: Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Device:
Function:
Offset:
Version:
4-5
0
09h
Intel 5000Z Chipset
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
4-7
0
09h
Intel 5000P Chipset
16
0, 2
09h
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
17
0
09h
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
21
0
09h
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
22
0
09h
Intel 5000P Chipset
Bit Attr Default
Description
23:16 RO
06h Base Class.
This field indicates the general device category. For the MCH, this field is hardwired
to 06h, indicating it is a “Bridge Device”.
Intel^® 5000X Chipset Memory Controller Hub (MCH) Datasheet
77