QG5000XSL9TH Datasheet, PDF (157/458 Pages) Intel Corporation – Intel 5000X Chipset Memory Controller Hub (MCH)

Register Description
Figure 3-5. PCI Express Hot-Plug Interrupt Flow
PEXHPINT
(HPGPEEN == 1)
Y
Intel® 5000P Chipset
Sends assert_HPGPE
message via DMI
N
Intel® 5000P Chipset
Sends desassert_HPGP
E message via
DMI when the
when the respective bits
PEXSLOTSTS str
cleared (wired-OR)
OR)
PEXSLOTCTRL[x].
N
HPINTEN = 1?
SW polls
status
Y
(MSICTRL[x].
MSIEN == 1) ?
N
PEXCMD[x].INTx
Disable == 1?
Y
Y
Intel® 5000P Chipset
Sends MSI per MSIAR
And MSIDR
Intel® 5000P Chipset
N _{Sends assert_INTx}
message via DMI
per INTP
Intel® 5000P Chipset
Sends desassert_INTx
message via DMI
when the
respective bits of
PEXSLOTSTS str
cleared (wired-
HPGPEEN
1
0
0
0
0
HPINTEN
x
1
1
1
0
MSIEN
x
1
0
0
x
INTx Disable
x
x
0
1
x
Output
assert_hpgpe
MSI
assert_intx
--
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Intel^® 5000X Chipset Memory Controller Hub (MCH) Datasheet
157