QG5000XSL9TH Datasheet, PDF (399/458 Pages) Intel Corporation – Intel 5000X Chipset Memory Controller Hub (MCH)

Testability
Figure 6-3. TAP Instruction Register
Figure 6-4 shows the operation of the instruction register during the Capture-IR, Shift-
IR and Update-IR states. Shaded areas indicate the bits that are updated. In
Capture-IR, the shift register portion of the instruction register is loaded in parallel with
the fixed value “0000001”. In Shift-IR, the shift register portion of the instruction
register forms a serial data path between TDI and TDO. In Update-IR, the shift register
contents are latched in parallel into the actual instruction register. Note that the only
time the outputs of the actual instruction register change is during Update-IR.
Therefore, a new instruction shifted into the TAP does not take effect until the Update-
IR state is visited.
Figure 6-4. TAP Instruction Register Operation
Figure 6-5 illustrates the timing when loading the BYPASS instruction (opcode
1111111b) into the TAP instruction register. Vertical arrows on the figure show the
specific clock edges on which the Capture-IR, Shift-IR and Update-IR actions actually
take place. Capture-IR (which preloads the instruction register with 0000001b) and
Shift-IR operate on rising edges of TCK, and Update- IR (which updates the actual
instruction register) takes place on the falling edge of TCK.
Intel^® 5000X Chipset Memory Controller Hub (MCH) Datasheet
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