QG5000XSL9TH Datasheet, PDF (46/458 Pages) Intel Corporation – Intel 5000X Chipset Memory Controller Hub (MCH)

Register Description
• Device 17: Device 17, Function 0 is routed to the Coherency Engine and Data
Manager registers. These devices reside at DID 25F1h.
• Device 19: Device 19, Function 0 is routed to the Debug and Miscellaneous
registers. These devices reside at DID 25F3h.
• Device 21: Device 21, Function 0, FBD Branch 0 Memory Map, Error Flag/Mask,
and Channel Control registers. These devices reside at DID 25F5h.
• Device 22: Device 22, Function 0, FBD Branch 1 Memory Map, Error Flag/Mask,
and Channel Control registers. These devices reside at DID 25F6h.
Figure 3-1. Conceptual Intel® 5000X chipset MCH PCI Configuration Diagram
Processor 0
Processor 1
PCI Config Window in I/O Space
4 bit
PCI Express
Port 4
4 bit
PCI Express
Port 5
4 bit
PCI Express
Port 6
4 bit
PCI Express
Port 7
PCI Express Port 4
Bridge Bus 0, Dev 4
PCI Express Port 5
Bridge Bus 0, Dev 5
PCI Express Port 6
Bridge Bus 0, Dev 6
PCI Express Port 7
Bridge Bus 0, Dev 7
PCI Express Port 2
Bridge Bus 0, Dev 2
PCI Express Port 3
Bridge Bus 0, Dev 3
Intel® 5000X
DMI
(PCI Express Bridge Bus 0,
Chipset
Dev 0)
DMI Interface (logical PCI Bus 0)
DMI
(PCI Express Bridge Bus 0,
Dev X)
4 bit
PCI Express
Port 2
4 bit
PCI Express
Port 3
PCI Express Port 0
Bridge Bus 0, Dev Y
PCI Express Port 1
Bridge Bus 0, Dev Z
LPC Device
Bus 0, Dev 31, Func 0
IDE Controller
Bus 0, Dev 31, Func 1
SMBus Controller
Bus 0, Dev 31, Func 3
USB Controllers
Bus 0, Dev 29,
Func 0,1,2,7
HI-PCI Bridge
Bus 0, Dev 30, Func 0
AC97 Controller
Bus 0, Dev 31, Func 5,6
LAN Controller
Bus n, Dev 8, Func 0
Intel® 631xESB/632xESB I/O Controller Hub
4 bit
PCI Express
Port 0
4 bit
PCI Express
Port 0
Primary PCI
Programmable
Bus #
46
Intel^® 5000X Chipset Memory Controller Hub (MCH) Datasheet