QG5000XSL9TH Datasheet, PDF (130/458 Pages) Intel Corporation – Intel 5000X Chipset Memory Controller Hub (MCH)

Register Description
3.8.8.33
PEXGCTRL - PCI Express Global Control Register
This 32-bit global register in the MCH implements chipset specific operations for
generalized control of all PCI Express events and activity such as Power Management,
hot-plug. There is only one register for all PCI Express ports and DMA Engine device
that controls related I/O operations.
Device:19
Function:0
Offset:17Ch
Version:Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Bit
Attr
31:18 RV
17:2
1
RV
RWST
0
RWC
Default
3FFFh
1385
0
0
Description
Timeout: Completion Time out
Internal timer for handling Outbound NP completion timeouts. This varies
based on the core clock frequency and the time at which the completion
structure is loaded relative to the timeout timer which is free-running. The
bounds of this roll over can be approximated as a Minimum of 6 or Max of 7
± few cycles) since there is a 3 bit counter whose roll over is tied to the
timeout timer
For 333 Mhz, the granularity of this timer viz. each increment is in the range
(9216 ns, 10,752 ns) giving a min/max value for a full face value of this
register field as (150.99 ms, 176.15 ms)
For 266 Mhz, the granularity of this timer viz. each increment is in the range
(11520 ns, 13440 ns) giving a min/max value for a full face value of this
register field as (188.73 ms, 220.19 ms)
BIOS/Software needs to set this field as appropriate for handling various
timeout conditions required by the system.
Note: For example with BNB running at 333 Mhz, for SMBUS protocols, the
maximum value recommended for this field is 0x744 (or 1860
decimal) to achieve a 20 ms timeout threshold (that is, 20 ms =~
10,752 * 1860) such that it provides headroom to the chipset for
the global SMBUS timeout of 25ms.
Example: With 0x744 as default and 333 MHz core clock,
1. Max timeout value: If bits 31:28 were set to 0x744 (1860d), the
timeout delay is calculated as follows:
1860*7 (for the rollovers)*512(lower 9 bits)*3.0ns (for 333 MHz) =
1860*107542=19.998ms=~20 ms
2. Min timeout value: If bits 31:28 were set to 0x744 (1860d), the delay
calculation would be like this:
1860*6 (too close to the limit, so missed full count for one rollover)*512
(lower 9 bits)*3.0 ns (for 333 MHz)= 17.141 ms=~17 ms
Reserved.
PME_TURN_OFF: Send PME Turn Off Message
When set, the Intel 5000 Chipset MCH will issue a PME Turn Off Message to
all enabled PCI Express ports excluding the ESI port. The Intel 5000 Chipset
MCH will clear this bit once the Message is sent.
• NOTE: In the Intel 5000 Chipset MCH implementation, an end device
that is D3 PM state and the Link being in L2 will not respond to any
transaction to the device until it is woken up by the WAKE# signal in the
platform. Under these conditions, if software sets the PME_Turn_OFF (bit
1) of this register, the Intel 5000 Chipset MCH will not send the message
until the Link is brought back into L0. i.e. PME_TURN_OFF bit will remain
set until the message is dispatched. Furthermore, a surprise link Down
error is logged.
† Expected Usage: Software should not set this bit if the link is already in
L2 prior.
PME_TO_ACK: Received PME Time Out Acknowledge Message
The Intel 5000P Chipset MCH sets this bit when it receives a PME_TO_ACK
Message from all enabled PCI Express ports excluding the ESI port. Software
will clear this bit when it handles the Acknowledge. Note that the ESI2 will
not generate a PME_TO_Ack based on the flow described in the ESI spec.
However, if a PME_TO_Ack is received at the Intel 5000P Chipset MCH ESI
port, it will be Master Aborted.
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Intel^® 5000X Chipset Memory Controller Hub (MCH) Datasheet