QG5000XSL9TH Datasheet, PDF (192/458 Pages) Intel Corporation – Intel 5000X Chipset Memory Controller Hub (MCH)

Register Description
Device:
Function:
Offset:
Version:
16
2
CCh
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Bit
Attr
Default
Description
7
RV
6
RWST
5
RWST
4
RWST
3
RWST
2
RWST
1
RWST
0
RWST
1
B8Msk: SF Coherency Error for BIL
1
B7Msk: Multiple ECC error in any of the ways during SF lookup
1
B6Msk: Single ECC error on SF lookup
1
B5Msk: Address Map Error
1
B4Msk: Virtual Pin Port Error
1
B3Msk: Coherency Violation Error for EWB
1
B2Msk: Multi-Tag Hit SF
1
B1Msk: DM Parity Error
3.8.13.25 ERR2_INT - Internal Error 2 Mask Register
This register enables the signaling of Err[2] when an error flag is set. Note that one and
only one error signal should be enabled in the ERR2_INT, ERR1_INT, ERR0_INT, and
MCERR_INT for each of the corresponding bits.
Device:
Function:
Offset:
Version:
16
2
D2h
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Bit
Attr
Default
Description
7
RWST
6
RWST
5
RWST
4
RWST
3
RWST
2
RWST
1
RWST
0
RWST
1
B8Err2Msk: SF Coherency Error for BIL
1
B7Err2Msk: Multiple ECC error in any of the ways during SF lookup
1
B6Err2Msk: Single ECC error on SF lookup
1
B5Err2Msk: Address Map Error
1
B4Err2Msk: SMBus Virtual Pin Error
1
B3Err2Msk: Coherency Violation Error for EWB
1
B2Err2Msk: Multi-Tag Hit SF
1
B1Err2Msk: DM Parity Error
3.8.13.26 ERR1_INT - Internal Error 1 Mask Register
This register enables the signaling of Err[1] when an error flag is set. Note that one and
only one error signal should be enabled in the ERR2_INT, ERR1_INT, ERR0_INT, and
MCERR_INT for each of the corresponding bits.
Device:
Function:
Offset:
Version:
16
2
D1h
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Bit
Attr
Default
Description
7
RWST
1
B8Err1Msk: SF Coherency Error for BIL
6
RWST
5
RWST
1
B7Err1Msk: Multiple ECC error in any of the ways during SF lookup
1
B6Err1Msk: Single ECC error on SF lookup
192
Intel^® 5000X Chipset Memory Controller Hub (MCH) Datasheet