QG5000XSL9TH Datasheet, PDF (97/458 Pages) Intel Corporation – Intel 5000X Chipset Memory Controller Hub (MCH)

Register Description
3.8.5.4
3.8.5.5
Device:
Function:
Offset:
Version:
16
0
44h
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Bit Attr
11 RWST
10:0 RV
Default
1
0h
Description
BUSPARK: Request Bus Parking Disable
If set, A[15]# is asserted and the processor may not park on the system
bus. Default is to disable busparking
Reserved
SPAD[3:0] - Scratch Pad Registers
These scratch pad registers each provide 32 read/writable bits that can be used by
software. They are also aliased to fixed memory addresses.
Device:
Function:
Offset:
Version:
16
0
DCh, D8h, D4h, D0h
Intel 5000P Chipset, Intel 5000V Chipset
Bit
31:0
Attr Default
Description
RW 00000000h Scratch Pad value. These bits have no effect on the hardware.
SPADS[3:0] - Sticky Scratch Pad
These sticky scratch pad registers each provide 32 read/writable bits that can be used
by software. They are also aliased to fixed memory addresses.
Device:
Function:
Offset:
Version:
16
0
ECh, E8h, E4h, E0h
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Bit
31:0
Attr
RWST
Default
Description
00000000h Scratch Pad value. These sticky bits have no effect on the hardware.
Intel^® 5000X Chipset Memory Controller Hub (MCH) Datasheet
97