QG5000XSL9TH Datasheet, PDF (356/458 Pages) Intel Corporation – Intel 5000X Chipset Memory Controller Hub (MCH)

Functional Description
it will allow communication between the two devices. Software will then be able to
interrogate the device at the other end of the link to determine why it failed to train at
a higher width.
5.13.7.2
8b/10b Encoder/Decoder and Framing
As a transmitter, the physical layer is responsible for encoding each byte into a 10 bit
data symbol before transmission across the link. Packet framing is accomplished by the
physical layer by adding special framing symbols (STP, SDP, END). PCI Express
implements the standard Ethernet and InfiniBand* 8b/10b encoding mechanism.
5.13.7.3 Elastic Buffers
Every PCI Express port implements an independent elastic buffer for each PCI Express
lane. The elastic buffers are required since the Intel 5000X chipset MCH and PCI
Express endpoints could be clocked from different sources. Clocks from different
sources will never be exactly the same. The outputs of the elastic buffers feed into the
deskew buffer.
Figure 5-22. PCI Express Elastic Buffer (x4 Example)
Local Clock = 2.501 GHz
Remote Clock = 2.499 GHz
5.13.7.4
The elastic buffer is eight symbols deep. This accounts for three clocks of
synchronization delay, the longest possible TLP allowed by the Intel 5000X chipset
MCH (256 B), a 600ppm difference between transmitter and receiver clocks, and worst
case skip ordered sequence interval of 1538, framing overheads, and a few symbols of
margin.
Deskew Buffer
Every PCI Express port implements a deskew buffer. The deskew buffer compensates
for the different arrival times for each of the symbols that make up a character. The
outputs of the deskew buffer is the data path fed into the Link layer.
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Intel^® 5000X Chipset Memory Controller Hub (MCH) Datasheet